Low Skew, Dual, Programmable 1-to-2
Differential-to-LVDS, LVPECL Fanout Buffer
ICS854S204I
DATA SHEET
General Description
The ICS854S204I is a low skew, high performance dual,
programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer.
The PCLKx, nPCLKx pairs can accept most standard differential
input levels. With the selection of SEL_OUT signal, outputs can be
selected be to either LVDS or LVPECL levels. The ICS854S204I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and bank skew characteristics make the
ICS854S204I ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
•
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•
•
•
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Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Power Supply Configuration Table
3.3V Operation
V
DD
= 3.3V
V
TAP
= nc
2.5V Operation
V
DD
= 2.5V
V
TAP
= 2.5V
SEL_OUT Function Table
SEL_OUT
0
1
Output Level
LVDS
LVPECL
Block Diagram
V
TAP
SEL_OUT
Pulldown
CLKA
Pulldown
nCLKA
Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
V
TAP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nPCLKB
PCLKB
QB0
nQB0
QB1
nQB1
V
DD
SEL_OUT
CLKB
Pulldown
nCLKB
Pullup
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS854S204BGI REVISION B NOVEMBER 18, 2011
1
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3, 4
5, 6
7
8
9
10
11, 12
13, 14
15
16
Name
PCLKA
nPCLKA
QA0, nQA0
QA1, nQA1
V
TAP
GND
SEL_OUT
V
DD
nQB1, QB1
nQB0, QB0
PCLKB
nPCLKB
Input
Input
Output
Output
Power
Power
Input
Power
Output
Output
Input
Input
Pulldown
Pullup
Pulldown
Type
Pulldown
Pullup
Description
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Power supply pin. Tie to V
DD
for 2.5V operation. For 3.3V operation, do not
connect.
Power supply ground.
Output select pin. Selects between LVDS or LVPECL outputs.
LVCMOS/LVTTL interface levels.
Power supply pin.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3. Clock Input Function Table
Inputs
PCLKA or
PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA or
nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA[0:1], QB[0:1]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQA[0:1], nQB[0:1]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information,
Wiring the Differential Input to Accept Single Ended Levels
section.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
2
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
10mA
15mA
92°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
120
Units
V
mA
Table 4B. LVDS Power Supply DC Characteristics,
V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
TAP
I
DD
I
TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
115
5
Units
V
V
mA
mA
Table 4C. LVPECL Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
66
Units
V
mA
Table 4D. LVPECL Power Supply DC Characteristics,
V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
TAP
I
DD
I
TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
60
5
Units
V
V
mA
mA
ICS854S204BGI REVISION B NOVEMBER 18, 2011
3
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 4E. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% or V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
SEL_OUT
SEL_OUT
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4F. Differential DC Characteristics,
V
DD
= 3.3V ± 5% or V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
PCLKA, PCLKB
nPCLKA, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
0.15
1.2
1.3
V
DD
Minimum
Typical
Maximum
150
10
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 4G. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
1.11
1.25
Minimum
247
Typical
350
Maximum
454
50
1.38
50
Units
mV
mV
V
mV
NOTE: Please refer to
Parameter Measurement Information
section for output information.
Table 4H. LVDS DC Characteristics,
V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
1.08
1.21
Minimum
247
Typical
350
Maximum
454
50
1.34
50
Units
mV
mV
V
mV
NOTE: Please refer to
Parameter Measurement Information
section for output information.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
4
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 4I. LVPECL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
V
DD
– 1.3
V
DD
– 2.0
0.6
Typical
Maximum
V
DD
– 0.8
V
DD
– 1.6
0.9
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DD
– 2V.
Table 4J. LVPECL DC Characteristics,
V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
V
DD
– 1.3
V
DD
– 2.0
0.6
Typical
Maximum
V
DD
– 0.8
V
DD
– 1.55
0.9
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DD
– 2V.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
5
©2011 Integrated Device Technology, Inc.
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