Low Skew, 1-to-16
LVCMOS/LVTTL Clock Generator
G
ENERAL
D
ESCRIPTION
The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator.
The device has 4 banks of 4 outputs and each bank can be
independently selected for
÷1
or
÷2
frequency operation. Each
bank also has its own power supply pins so that the banks can
operate at the following different voltage levels: 3.3V, 2.5V, and
1.8V. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the
output frequency of each bank. The output banks can be
independently selected for
÷1
or
÷2
operation. The bank enable
inputs, CLK_ENA:CLK_END, support enabling and disabling
each bank of outputs individually. The CLK_ENA:CLK_END
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the
÷1/÷2
flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
The 87016 is characterized to operate with the core at
3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed
bank, output, and part-to-part skew characteristics make
the 87016 ideal for those clock applications demanding
well-defined performance and repeatability.
87016
DATASHEET
F
EATURES
• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or
LVCMOS clock input
•
CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for
÷1
or
÷2
operation
• Independent output bank voltage settings for 3.3V, 2.5V,
or 1.8V operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 30ps (maximum)
• Part-to-part skew: 750ps (maximum)
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Pin LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
.
01/21/20
1
©20tegrated Device Technology, Inc.
87016 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 48
2
3
4
5
6
7
8
9
10
11
12, 16, 20, 24, 28,
32, 36, 40, 44
13, 15, 17, 19
14, 18
21, 23, 25, 27
22, 26
29, 31, 33, 35
30, 34
37, 39, 41, 43
38, 42
45
46
47
Name
V
DD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
nMR/OE
GND
QD3, QD2,
QD1, QD0
V
DDOD
QC3, QC2,
QC1, QC0
V
DDOC
QB3, QB2,
QB1, QB0
V
DDOB
QA3, QA2,
QA1, QA0
V
DDOA
CLK_SEL
nCLK1
CLK1
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Power
Output
Power
Input
Input
Input
Type
Description
Positive supply pins.
Pulldown LVCMOS / LVTTL clock input.
Controls frequency division for Bank A outputs.
Pullup
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs
Pullup
LVCMOS / LVTTL interface levels..
Controls frequency division for Bank C outputs.
Pullup
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank D outputs.
Pullup
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH.
Pullup
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Output enable for Bank B outputs. Active HIGH.
Pullup
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Output enable for Bank C outputs. Active HIGH.
Pullup
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Output enable for Bank D outputs. Active HIGH.
Pullup
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the
Pullup
outputs to high impedance. LVCMOS / LVTTL interface levels.
Power supply ground.
Bank D outputs. LVCMOS / LVTTL interface levels.
Output Bank D power supply pins.
Bank C outputs. LVCMOS / LVTTL interface levels.
Output Bank C power supply pins.
Bank B outputs. LVCMOS / LVTTL interface levels.
Output Bank B power supply pins.
Bank A outputs. LVCMOS / LVTTL interface levels.
Output Bank A power supply pins.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
2
REVISION C 06/26/15
87016 DATA SHEET
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
, V
DDOx
= 3.465V
V
DD
= 3.465, V
DDOx
= 2.625V
V
DD
= 3.465, V
DDOx
= 1.89V
7
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, and V
DDOD
.
Test Conditions
Minimum
Typical
4
51
18
20
30
Maximum
Units
pF
kΩ
pF
pF
pF
Ω
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
CLK_ENx
X
1
1
0
Outputs
Bank X
Qx Frequency
Hi Z
N/A
Active
Active
Low
fIN/2
fIN
N/A
nMR/OE
0
1
1
1
DIV_SELx
X
0
1
X
01/21/20
3
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
87016 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDOx
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
V
DDOx
I
DD
I
DDOx
Parameter
Positive Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Output Supply Current; NOTE 2
Test Conditions
Minimum
3.135
3.135
2.375
1.71
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.89
100
15
Units
V
V
V
V
mA
mA
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, and V
DDOD
. NOTE 2: I
DDOx
denotes I
DDOA
, I
DDOB
, I
DDOC
, and I
DDOD
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
Parameter
Input
High Voltage
DIV_SELA:DIV_SELD,
CLK_ENA:CLK_END,
nMR/OE, CLK_SEL
CLK0
Input
Low Voltage
DIV_SELA:DIV_SELD,
CLK_ENA:CLK_END,
nMR/OE, CLK_SEL
CLK0
CLK_ENA:CLK_END,
DIV_SELA:DIV_SELD,
Input
High Current nMR/OE
CLK0, CLK_SEL
Input
Low Current
CLK_ENA:CLK_END,
DIV_SELA:DIV_SELD,
nMR/OE
CLK0, CLK_SEL
DDOx
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V + 0.3
DD
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IH
V + 0.3
DD
V
IL
0.8
1.3
5
150
I
IH
V = V = 3.465V
DD
IN
V = V = 3.465V
DD
IN
I
IL
V = 3.465V, V = 0V
DD
IN
-150
-5
2.6
1.8
V
DDOx
- 0.45
DD
V = 3.465V, V = 0V
DD
IN
V = 3.3V ± 5%; NOTE 2
V
OH
Output High Voltage; NOTE 1
DDOx
V = 2.5V ± 5%; NOTE 2
DDOx
V = 1.8V ± 5%; NOTE 2 I =
-2mA
OH
V = 3.3V ± 5%; NOTE 2
DDOx
0.5
0.5
0.45
-5
5
V
V
V
µA
µA
V
OL
Output Low Voltage; NOTE 1
DDOx
V = 2.5V ± 5%; NOTE 2
DDOx
V = 1.8V ± 5%; NOTE 2 I =
2mA
OL
I
OZL
I
OZH
Output Tristate Current Low
Output Tristate Current High
NOTE 1: Outputs terminated with 50W to V
DDOX
/2. See Parameter Measurement Information, Output Load Test Circuit.
NOTE 2: V
DDOx
denotes V
DDOA
, V
DDOB,
V
DDOC
and V
DDOD
.
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
4
REVISION C 06/26/15
87016 DATA SHEET
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK1
CLK1
nCLK1
CLK1
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
85°C
X
Symbol
f
MAX
tp
LH
tsk(b)
tsk(o)
tsk(pp)
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay,
Low to High
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Test Conditions
Minimum
2.8
2.9
Typical
3.2
3.4
Maximum
250
3.7
3.9
30
150
750
Units
MHz
ns
ns
ps
ps
ps
ps
%
%
ns
ns
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Part-to-Part Skew; NOTE 5, 7
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
Measured on the Rising Edge
Measured on the Rising Edge
20% to 80%
f < 175MHz
f
≥
175MHz
200
45
40
700
55
60
10
10
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
DDOX
/2.
NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal
load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
01/21/20
5
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
