L
OW
S
KEW
÷1, ÷2
LVCMOS / LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87949I-01 is a low skew, ÷1, ÷2 Clock Generator.
The ICS87949I-01 has selectable single ended clock or
LVPECL clock inputs. The single ended clock input accepts
LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can
accept LVPECL, CML, or SSTL input levels. The low
impedance LVCMOS/LVTTL outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 15 to 30 by utilizing
the ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the
÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master
reset input, MR/nOE, resets the internal frequency dividers
and also controls the active and high impedance states of
all outputs.
The ICS87949I-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and
part-to-part skew characteristics make the ICS87949I-01 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
ICS87949I-01
F
EATURES
• 15 single ended LVCMOS/LVTTL outputs,
7Ω typical output impedance
• Selectable LVCMOS/LVTTL or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 250ps (maximum)
• Part-to-part skew: 1ns (maximum)
• Full 3.3V or mixed 3.3V core/2.5V output supply
• -40°C to 85°C ambient operating temperature
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
B
LOCK
D
IAGRAM
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
1
DIV_SELA
0
QB0:QB2
1
DIV_SELB
0
QC0:QC3
1
DIV_SELC
0
QD0:QD5
1
DIV_SELD
MR/nOE
87949AYI-01
P
IN
A
SSIGNMENT
GND
GND
GND
GND
V
DDB
V
DDA
V
DDB
QA0
QA1
QB0
QB1
QB2
0
0
1
1
÷1
÷2
R
0
QA0, QA1
MR/nOE
CLK_SEL
V
DD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
QD0
V
DDD
QD1
GND
QD2
V
DDD
QD3
GND
QD4
V
DDD
nc
GND
QC0
V
DDC
QC1
GND
QC2
V
DDC
QC3
GND
GND
QD5
ICS87949I-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.idt.com
1
REV. A AUGUST 10, 2010
L
OW
S
KEW
÷1, ÷2
LVCMOS / LVTTL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
Name
Type
Description
Active HIGH Master Reset. Active LOW output enable.
When logic HIGH, the internal dividers are reset and
Pulldown the outputs are tri-stated (HiZ). When logic LOW, the
internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1. When
Pulldown
LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Positive supply pin.
Pullup
Pullup
LVCMOS / LVTTL clock inputs.
Inver ting differential LVPECL clock input.
Pulldown Non-inver ting differential LVPECL clock input.
Pulldown PCLK select input. LVCMOS / LVTTL interface levels.
Controls frequency division for Bank A outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank D outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Power supply ground.
Bank D outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Positive supply pins for Bank D outputs.
Bank C outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Positive supply pins for Bank C outputs.
No connect.
Positive supply pins for Bank B outputs.
Bank B outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Bank A outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Positive supply pins for Bank A outputs.
ICS87949I-01
1
MR/nOE
Input
2
3
4, 5
6
7
8
9
10
11
12
13, 14, 18, 22,
26, 27, 31, 35,
39, 43, 44, 48
15, 17, 19
21, 23, 25
16, 20, 24,
28, 30, 32, 34
29, 33
36
37, 41
38, 40, 42
45, 47
46
CLK_SEL
V
DD
CLK0, CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
QD0, QD1, QD2,
QD3, QD4, QD5
V
DDD
QC3, QC2, QC1, QC0
V
DDC
nc
V
DDB
QB2, QB1, QB0
QA1, QA0
V
DDA
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Power
Output
Power
Unused
Power
Output
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI-01
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2
REV. A AUGUST 10, 2010
L
OW
S
KEW
÷1, ÷2
LVCMOS / LVTTL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance (per output);
NOTE 1
Output Impedance
V
DD
, V
DDx
= 3.465V
V
DD
, V
DDx
= 2.625V
5
Test Conditions
Minimum Typical
4
51
51
23
16
7
12
Maximum
Units
pF
KΩ
KΩ
pF
pF
Ω
ICS87949I-01
NOTE 1: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
, V
DDD
.
T
ABLE
3. F
UNCTION
T
ABLE
MR/nOE
1
0
0
0
0
0
0
0
0
DIV_SELA
X
0
1
X
X
X
X
X
X
Inputs
DIV_SELB
X
X
X
0
1
X
X
X
X
DIV_SELC
X
X
X
X
X
0
1
X
X
DIV_SELD
X
X
X
X
X
X
X
0
1
QA0:QA1
Hi Z
fIN/1
fIN/2
Active
Active
Active
Active
Active
Active
Outputs
QB0:QB2
QC0:QC3
Hi Z
Hi Z
Active
Active
Active
Active
fIN/1
Active
fIN/2
Active
Active
fIN/1
Active
fIN/2
Active
Active
Active
Active
QD0:QD5
Hi Z
Active
Active
Active
Active
Active
Active
fIN/1
fIN/2
87949AYI-01
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3
REV. A AUGUST 10, 2010
L
OW
S
KEW
÷1, ÷2
LVCMOS / LVTTL C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS87949I-01
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
X
Symbol Parameter
V
DD
Positive Supply Voltage
Output Supply Voltage; NOTE 1
V
DDx
Power Supply Current
I
DD
Output Supply Current; NOTE 2
I
DDx
NOTE 1: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
, V
DDD
.
NOTE 2: I
DDx
denotes I
DDA
, I
DDB
, I
DDC
, I
DDD
.
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
60
20
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
X
Symbol
Parameter
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA: DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
IH
Input High Current
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
2.6
I
IL
V
OH
V
OL
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
87949AYI-01
www.idt.com
4
REV. A AUGUST 10, 2010
L
OW
S
KEW
÷1, ÷2
LVCMOS / LVTTL C
LOCK
G
ENERATOR
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
X
ICS87949I-01
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
-5
-150
0.3
1
V
DD
Peak-to-Peak Input Voltage
V
V
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
X
Symbol
f
MAX
t
PD
Parameter
Input Frequency
Propagation Delay, NOTE 1
Bank Skew; NOTE 2, 6
Output Skew; NOTE 3, 6
Par t-to-Par t Skew; NOTE 4, 6
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
Output Enable Time;NOTE 5
Test Conditions
Minimum
2.1
Typical
Maximum
250
5
100
300
1
Units
MHz
ns
ps
ps
ns
ps
%
ns
ns
t
sk(b)
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
t
EN
Measured on rising edge at V
DDx
/2
Measured on rising edge at V
DDx
/2
Measured on rising edge at V
DDx
/2
20% to 80%
Measured with outputs in ÷1
f = 10MHz
400
40
950
60
5
Output Disable Time;NOTE 5
f = 10MHz
5
t
DIS
All parameters measured at
≤
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at V
DDx
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI-01
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5
REV. A AUGUST 10, 2010
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