Low Skew, 1-to-5 Differential-to-2.5V, 3.3V
LVPECL Fanout Buffer
ICS85314I-11
DATA SHEET
General Description
The ICS85314I-11 is a low skew, high performance
1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer.
HiPerClockS™
The ICS85314I-11 has two selectable differential clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can
accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt clock pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Features
•
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Five differential 2.5V/3.3V LVPECL outputs
Selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Propagation delay: 1.8ns (maximum)
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Guaranteed output and part-to-part skew characteristics make the
ICS85314I-11 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
nCLK_EN
Pulldown
Pin Assignment
D
Q
CK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nCLK1
CLK1
RESERVED
nCLK0
CLK0
CLK_SEL
V
EE
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
0
Q0
nQ0
1
Q1
nQ1
Q2
ICS85314I-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
CLK_SEL
Pulldown
nQ2
Q3
nQ3
Q4
nQ4
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
ICS85314AGI-11 REVISION E MAY 4, 2010
1
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11
12
13
14
15
16
17
18, 20
19
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
EE
CLK_SEL
CLK0
nCLK0
RESERVED
CLK1
nCLK1
V
CC
nCLK_EN
Output
Output
Output
Output
Output
Power
Input
Input
Input
Reserve
Input
Input
Power
Input
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Reserved pin.
Non-inverting differential clock input.
Inverting differential clock input.
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input. When
HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS85314AGI-11 REVISION E MAY 4, 2010
2
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
nCLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q[0:4]
Enabled
Enabled
Disabled; LOW
Disabled; LOW
Outputs
nQ[0:4]
Enabled
Enabled
Disabled; HIGH
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the
active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described in Table 3B.
nCLK[0:1]
CLK[0:1]
Disabled
Enabled
nCLK_EN
nQ[0:4]
Q[0:4]
Figure 1. nCLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
0
1
nCLK0 or nCLK1
1
0
Q[0:4]
LOW
HIGH
Outputs
nQ[0:4]
HIGH
LOW
Input to Output Mode
Differential-to-Differential
Differential-to-Differential
Polarity
Non-Inverting
Non-Inverting
ICS85314AGI-11 REVISION E MAY 4, 2010
3
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
20 Lead SOIC
20 Lead TSSOP
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
73.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
80
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, CLK_SEL
nCLK_EN, CLK_SEL
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Range; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V
NOTE 2: Common mode voltage is defined as V
IH
.
ICS85314AGI-11 REVISION E MAY 4, 2010
4
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 4D. LVPECL DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50Ω to V
CC
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tp
LH
tsk(o)
tjit(θ)
tsk(pp)
t
S
t
H
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random);
NOTE 4
Part-to-Part Skew; NOTE 3, 5
Setup Time
Hold Time
Output Rise/Fall Time
Output Duty Cycle Skew
nCLK_EN to CLK
nCLK_EN to CLK
20% to 80%
ƒ
≤
700MHz
50
50
200
45
700
55
155.52MHz,
Integration Range: 12kHz - 20MHz
0.05
350
ƒ
≤
700MHz
1.0
1.4
Test Conditions
Minimum
Typical
Maximum
700
1.8
30
Units
MHz
ns
ps
ps
ps
ps
ps
ps
%
NOTE: All parameters measured at ƒ
max
unless otherwise noted.
NOTE: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to Phase Noise Plot.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS85314AGI-11 REVISION E MAY 4, 2010
5
©2010 Integrated Device Technology, Inc.
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