PRELIMINARY
PCI EXPRESS™/JITTER ATTENUATOR
ICS874002-02
G
ENERAL
D
ESCRIPTION
The ICS874002-02 is a high perfor mance
Differential-to-LVDS Jitter Attenuator designed for
HiPerClockS™
use in PCI Express™ systems. In some PCI
Express™ systems, such as those found in desktop
PCs, the PCI Express™ clocks are generated from
a low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter
components from the PLL synthesizer and from the system
board. The ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz
and 3MHz. The 2.2MHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 3MHz bandwidth provides the best track-
ing skew and will pass most spread profiles, but the jitter
attenuation will not be as good as the lower bandwidth modes.
The 874002-02 can be set for differential modes using the
F_SELx pins as shown in Table 3C.
F
EATURES
•
Two differential LVDS output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 640MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 50ps (maximum) design target
•
3.3V operating supply
•
Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
The ICS874002-02 uses IDT’s 3
rd
Generation FemtoClock
TM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
PLL B
ANDWIDTH
(T
YPICAL
)
BW_SEL
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
2
nQ0
V
DDO
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
V
DDO
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
F_SEL[1:0]
Pullup:Pulldown
BW_SEL
Pulldown
0 = 2.2MHz
1 = 3MHz
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640 MHz
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q0
nQ0
ICS874002-02
20-Lead TSSOP
Q1
nQ1
FB_IN
Pulldown
nFB_IN
Pullup
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
÷5 (fixed)
FB_OUT
nFB_OUT
MR
Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
PCI EXPRESS/JITTER ATTENUATOR
1
ICS874002AG-02 REV. A NOVEMBER 12, 2008
ICS874002-02
PCI EXPRESS™/JITTER ATTENUATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 20
2, 19
3,
4
5
Name
nQ0, Q0
V
DDO
FB_OUT,
nFB_OUT
MR
Power
Output
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential feedback output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx, FB_OUT) to go low and the inver ted
Pulldown
outputs (nQx, nFB_OUT) to go high. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bandwidth select input. LVCMOS/LVTTL interface levels.
Pulldown
See Table 3B.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Analog supply pin.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Pullup
See Table 3A.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
Pulldown Non-inver ting differential feedback input.
Pullup
Inver ting differential feedback input.
Differential output pair. LVDS interface levels.
Input
6
7
8
9
10
11
12
13
14
15
16
17, 18
BW_SEL
F_SEL1
V
DDA
F_SEL0
V
DD
OE
CLK
nCLK
GN D
FB_IN
nFB_IN
nQ1, Q1
Input
Input
Power
Input
Power
Input
Input
Input
Power
Input
Input
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Input
OE
0
1
Outputs
Q[0:1] / nQ[0:1]
High Impedance
Enabled
FB_OUT/nFB_OUT
Enabled
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
C
ONTROL
T
ABLE
Input
BW_SEL
0
1
PLL Bandwidth
2.2MHz (default)
3MHz
T
ABLE
3C. F_SEL
X
F
UNCTION
T
ABLE
Input Frequency
(MHz)
100
100
100
100
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
Divider
5
4
2
1
Output Frequency
(MHz)
100
12 5
250 (default)
500
IDT
™
/ ICS
™
PCI EXPRESS/JITTER ATTENUATOR
2
ICS874002AG-02 REV. A NOVEMBER 12, 2008
ICS874002-02
PCI EXPRESS™/JITTER ATTENUATOR
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
86.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
3.135
Typical
3.3
3.3
3.3
65
10
60
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
V
IM
I
IH
Input High Voltage
F_SEL, OE, MR
BW_SEL
F_SEL, OE, MR
BW_SEL
BW_SEL
OE, F_SEL1
BW_SEL,
F_SEL0, MR
OE, F_SEL1
BW_SEL,
F_SEL0, MR
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
V
DD
/2 - 0.1
Test Conditions
Minimum
2
V
DD
- 0.4
-0.3
0.8
V
DD
+ 0.4
V
DD
/2 +0.1
5
150
Typical
Maximum
V
DD
+ 0.3
Units
V
V
V
V
V
µA
µA
µA
µA
Input Low Voltage
Input Mid Voltage
Input High Current
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
1.3
5
150
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
DD
- 0.85
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is V
DD
+ 0.3V.
IDT
™
/ ICS
™
PCI EXPRESS/JITTER ATTENUATOR
3
ICS874002AG-02 REV. A NOVEMBER 12, 2008
ICS874002-02
PCI EXPRESS™/JITTER ATTENUATOR
PRELIMINARY
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
420
50
1.35
50
Maximum
Units
mV
mV
V
mV
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
Parameter
Output Frequency
Cycle-to-Cycle Jitter ; NOTE 1
Output Skew; NOTE 2, 3
Static Phase Offset; NOTE 4
Output Rise/Fall Time
20% to 80%
350
Test Conditions
Minimum
98
Typical
Maximum
640
50
Units
MHz
ps
ps
ps
ps
t
jit(cc)
tsk(o)
tsk(Ø)
t
R
/ t
F
odc
Output Duty Cycle
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
Minimum and maximum values are design target specs.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable.
IDT
™
/ ICS
™
PCI EXPRESS/JITTER ATTENUATOR
4
ICS874002AG-02 REV. A NOVEMBER 12, 2008
ICS874002-02
PCI EXPRESS™/JITTER ATTENUATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
V
DD,
V
DDO
Qx
V
DDA
nCLK,
nFB_IN
V
PP
Cross Points
V
LVDS
nQx
CMR
CLK,
FB_IN
GND
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQy
Qy
nQ0, nQ1
Q0, Q1
tcycle
n
t
cycle
➤
tjit(cc)
=
tcycle
n –
tcycle
n+1
1000 Cycles
tsk(o)
O
UTPUT
S
KEW
C
YCLE
-
TO
-C
YCLE
J
ITTER
nCLK
CLK
nFB_IN
FB_IN
V
OH
V
OL
V
OH
V
OL
nQ0, nQ1
Q0, Q1
t
PW
t
PERIOD
➤
t(Ø)
odc =
t
PW
t
PERIOD
t
(Ø)
mean
= Static Phase Offset
(where
t
(Ø) is any random sample, and
t
(Ø)
mean
is the average
of the sampled cycles measured on controlled edges)
S
TATIC
P
HASE
O
FFSET
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
IDT
™
/ ICS
™
PCI EXPRESS/JITTER ATTENUATOR
5
ICS874002AG-02 REV. A NOVEMBER 12, 2008
➤
➤
➤
tcycle
n+1
t
cycle n+1
➤
x 100%
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
