LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V,
3.3V LVPECL/ECL FANOUT BUFFER
ICS853031
G
ENERAL
D
ESCRIPTION
The ICS853031 is a low skew, high performance
1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS853031 has two selectable clock in-
puts. The CLK, nCLK pair can accept most standard differen-
tial input levels. The PCLK, nPCLK pair can accept LVPECL,
LVDS, CML, or SSTL input levels. The clock enable is inter-
nally synchronized to eliminate runt pulses on the outputs dur-
ing asynchronous assertion/deassertion of the clock enable
pin.
F
EATURES
•
Nine differential 2.5V/3.3V LVPECL/ECL outputs
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
•
PCLK, nPCLK supports the following input types:
LVPECL, LVDS, CML, SSTL
•
Output frequency: 1.6GHz (typical)
•
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK or
nPCLK inputs
•
Output skew: 20ps (typical)
•
Part-to-part skew: 75ps (typical)
•
Propagation delay: 875ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.465V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
IC
S
Guaranteed output skew and part-to-part skew characteristics
make the ICS853031 ideal for high performance workstation and
server applications.
B
LOCK
D
IAGRAM
CLK_EN
P
IN
A
SSIGNMENT
V
CCO
V
CCO
nQ0
nQ1
nQ2
Q0
Q1
Q2
D
Q
LE
32 31 30 29 28 27 26 25
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Vcco
nQ8
Q8
nQ7
Q7
nQ6
Q6
Vcco
CLK
nCLK
PCLK
nPCLK
0
1
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CCO
CLK_SEL
ICS853031
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
IIDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
1
ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9, 16, 17,
24, 25, 32
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
Name
V
CC
CL K
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
V
CCO
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Power
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Type
Power
Pullup
Description
Positive supply pin.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown
When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
Output supply pins.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
50
50
Maximum
Units
kΩ
kΩ
IDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
2
ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Sourced
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0:Q8
Disabled; LOW
Disabled; LOW
Enabled
Outputs
nQ0:nQ8
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
nCLK, nPCLK
CLK, PCLK
Disabled
Enabled
CLK_EN
nQ0:nQ8
Q0:Q8
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q8
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ8
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
IDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
3
ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V
-4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-40°C to +85°C
-65°C to 150°C
47.9°C/W (0 lfpm)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to
the device. These ratings are stress specifications only.
Functional operation of product at these conditions or
any conditions beyond those listed in the
DC Charac
teristics
or
AC Characteristics
is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
Symbol
V
CC
V
CCO
I
EE
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.465
3.465
85
Units
V
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
Input High Current
Input Low Current
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
IN
= 0V, V
CC
= 3.465V or 2.625V
V
IN
= 0V, V
CC
= 3.465V or 2.625V
-150
-50
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.465
0.8
10
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
(CLK, nCLK)
,
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
-
5
0
-150
-40°C
Min
Typ
Max
150
10
-
5
0
-150
25°C
Min
Typ
Max
15 0
10
-
5
0
-150
85°C
Min
Typ
Ma x
150
10
Units
µA
µA
µA
µA
0.15
1.3
0.15
1.3
0.15
Peak-to-Peak Input Voltage
Input High Voltage
V
EE
+ 0.7
V
CC
- 0.85 V
EE
+ 0.7
V
CC
- 0.85 V
EE
+ 0.7
Common Mode Range;
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
1.3
V
CC
- 0.85
V
V
IDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
4
ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
(PCLK, nPCLK)
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
Input Low Current
PCLK
-40°C
Min
2.175
1.405
0.15
1.2
Typ
2.275
1.545
0. 8
Max
2.38
1.68
1. 3
V
CC
150
10
-50
-50
Mi n
2.225
1.425
0.15
1.2
25°C
Typ
2.295
1.52
0.8
Max
2.37
1.615
1.3
V
CC
150
10
-50
Min
2.22
1.44
0.15
1.2
85°C
Typ
2.295
1.535
0.8
Max
2.365
1.63
1.3
V
CC
150
10
Units
V
V
V
V
µA
µA
µA
µA
nPCLK
-150
-15 0
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ± 0.165V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
(PCLK, nPCLK)
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
Input Low Current
PCLK
-40°C
Min
1.375
0.605
0.15
1.2
Typ
1.475
0.745
0. 8
Max
1.58
0.88
1. 3
V
CC
150
10
-10
-10
Mi n
1.425
0.625
0.15
1.2
25°C
Typ
1.495
0.72
0.8
Max
1.57
0.815
1.3
V
CC
150
10
-10
Min
1.42
0.64
0.15
1.2
85°C
Typ
1.495
0.735
0.8
Max
1.565
0.83
1.3
V
CC
150
10
Units
V
V
V
V
µA
µA
µA
µA
nPCLK
-150
-15 0
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ± 0.125V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
IDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
5
ICS853031AY REV. C AUGUST 12, 2008
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
