LTC2351-14
6 Channel, 14-Bit, 1.5Msps
Simultaneous Sampling ADC
with Shutdown
DESCRIPTIO
The LTC
®
2351-14 is a 14-bit, 1.5Msps ADC with six
simultaneously sampled differential inputs. The device
draws only 5.5mA from a single 3V supply, and comes in
a tiny 32-pin (5mm
×
5mm) QFN package. A SLEEP
shutdown mode further reduces power consumption to
12µW. The combination of low power and tiny package
makes the LTC2351-14 suitable for portable applications.
The LTC2351-14 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or
±1.25V
bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
FEATURES
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■
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■
■
■
■
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■
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■
1.5Msps ADC with 6 Simultaneously Sampled
Differential Inputs
250ksps Throughput per Channel
75dB SINAD
Low Power Dissipation: 16.5mW
3V Single Supply Operation
2.5V Internal Bandgap Reference, Can be Overdriven
with External Reference
3-Wire SPI-Compatible Serial Interface
Internal Conversion Triggered by CONV
SLEEP (12µW) Shutdown Mode
NAP (4.5mW) Shutdown Mode
0V to 2.5V Unipolar, or
±1.25V
Bipolar Differential
Input Range
83dB Common Mode Rejection
Tiny 32-Pin (5mm
×
5mm) QFN Package
APPLICATIO S
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Multiphase Power Measurement
Multiphase Motor Control
Data Acquisition Systems
Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRA
CH5
–
21
CH5
+
20
19
CH4
–
18
CH4
+
17
10µF
CH3
–
15
CH3
+
14
12
13
CH2
–
11
CH2
+
10
9
CH1
–
8
CH1
+
7
6
5
CH0
–
4
CH0
+
24
V
CC
16
–
–
S AND H
–
–
–
–
S AND H
S AND H
S AND H
S AND H
S AND H
1.5Msps
14-BIT ADC
MUX
TIMING
LOGIC
30
32
31
33
22
GND
10µF
23
V
REF
29
BIP
26
27
28
235114 TA01
2.5V
REFERENCE
U
W
U
3V
V
DD
25
14-BIT LATCH 0
14-BIT LATCH 1
14-BIT LATCH 2
14-BIT LATCH 3
14-BIT LATCH 4
14-BIT LATCH 5
OV
DD
3V
SD0
OGND
0.1µF
+
+
+
+
+
+
THREE-
STATE
SERIAL
OUTPUT
PORT
3
1
2
CONV
SCK
DGND
SEL2 SEL1 SEL0
235114f
1
LTC2351-14
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
16 15 14 13 12 11 10 9
CH4
+
17
CH4
–
Supply Voltage (V
DD
, V
CC
, OV
DD
) .............................. 4V
Analog and V
REF
Input Voltages
(Note 3) ................................... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltages .................. – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC2351C-14 .......................................... 0°C to 70°C
LTC2351I-14 ...................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
ORDER PART
NUMBER
8
7
6
CH1
–
CH1
+
GND
CH0
–
CH0
+
OV
DD
OGND
SDO
CH3
–
CH3
+
CH2
–
CH2
+
GND
GND
GND
GND
18
GND 19
CH5
CH5
+
–
LTC2351CUH-14
LTC2351IUH-14
20
21
33
5
4
3
2
1
GND 22
V
REF
23
V
CC
24
25 26 27 28 29 30 31 32
QFN PART
MARKING
235114
V
DD
BIP
SEL2
SEL1
SEL0
CONV
QFN PACKAGE
32-PIN (5mm
×
5mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 34°C/ W
EXPOSED PIN IS GND (PAD 33)
MUST BE SOLDERED TO PCB
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Offset Match from CH0 to CH5
Range Error
Range Match from CH0 to CH5
Range Tempco
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
●
DGND
SCK
MIN
14
–3
–4.5
–3
–12
–5
●
●
●
TYP
±1
±1
±0.5
±2
±1
±15
±1
MAX
3
4.5
3
12
5
UNITS
Bits
LSB
mV
mV
mV
mV
ppm/°C
ppm/°C
(Note 5)
(Note 4)
(Note 4)
Internal Reference (Note 4)
External Reference
A ALOG I PUT
SYMBOL PARAMETER
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
t
SK
CMRR
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
2.7V
≤
V
DD
≤
3.6V, Unipolar
2.7V
≤
V
DD
≤
3.6V, Bipolar
(Note 8)
●
MIN
TYP
0 to 2.5
±1.25
0 to V
DD
MAX
UNITS
V
V
V
Analog Differential Input Range (Notes 3, 8, 9)
Analog Common Mode + Differential
Input Range
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Channel to Channel Aperture Skew
Analog Input Common Mode Rejection Ratio
1
13
39
1
0.3
200
(Note 6)
●
f
IN
= 100kHz, V
IN
= 0V to 3V
f
IN
= 10MHz, V
IN
= 0V to 3V
–83
–67
235114f
2
U
µA
pF
ns
ns
ps
ps
dB
dB
W
U
U
W W
W
U
U
U
LTC2351-14
DY A IC ACCURACY
SYMBOL
SINAD
THD
SFDR
IMD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
Full Power Bandwidth
Full Linear Bandwidth
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
100kHz Input Signal
300kHz Input Signal
100kHz First 5 Harmonics
300kHz First 5 Harmonics
100kHz Input Signal
300kHz Input Signal
0.625V
P-P
, 833kHz into CH0+, 0.625V
P-P
, 841kHz into CH0–
Bipolar Mode. Also Applicable to Other Channels
V
REF
= 2.5V (Note 17)
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(–3dBFS) (Note 15)
S/(N + D)
≥
68dB, Bipolar Differential Input
●
●
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
External V
REF
Input Range
CONDITIONS
I
OUT
= 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3V
V
OUT
= V
DD
= 3V
CONDITIONS
V
DD
= 3.3V
V
DD
= 2.7V
V
IN
= 0V to V
DD
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
●
●
●
U
U
U
W U
U
MIN
71
–80
TYP
75
75
–90
–86
90
86
–80
0.7
50
5
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
LSB
RMS
MHz
MHz
U
T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
TYP
2.5
15
600
0.2
2
2.55
V
DD
MAX
UNITS
V
ppm/°C
µV/V
Ω
ms
V
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
Ext C
REF
= 10µF
TYP
MAX
0.6
±10
UNITS
V
V
µA
pF
V
V
V
µA
pF
mA
mA
2.4
5
V
DD
= 3V, I
OUT
= – 200µA
V
DD
= 2.7V, I
OUT
= 160µA
V
DD
= 2.7V, I
OUT
= 1.6mA
V
OUT
= 0V and V
DD
●
●
●
2.5
2.9
0.05
0.4
±10
1
20
15
235114f
3
LTC2351-14
POWER REQUIRE E TS
SYMBOL
V
DD
, V
CC
I
DD
+ I
CC
PARAMETER
Supply Voltage
Supply Current
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= V
CC
= 3V.
CONDITIONS
Active Mode, f
SAMPLE
= 1.5Msps
Nap Mode
Sleep Mode
Active Mode with SCK, f
SAMPLE
= 1.5Msps
●
●
PD
Power Dissipation
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V.
SYMBOL
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum High or Low CONV Pulse Width
SCK↑ to Sample Mode
CONV↑ to Hold Mode
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK↑ to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
(Note 16)
(Notes 6, 17)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
2
2
CONDITIONS
●
●
●
TI I G CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2:
All voltage values are with respect to ground GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and range specifications apply for a single-ended CH0
+
–
CH5
+
input with CH0
–
– CH5
–
grounded and using the internal 2.5V
reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between CHx
+
and CHx
–
, x = 0–5.
4
U W
MIN
2.7
TYP
3.0
5.5
1.5
4.0
16.5
MAX
3.6
8
2
15
UNITS
V
mA
mA
µA
mW
UW
MIN
250
TYP
MAX
UNITS
kHz
4
40
96
2
3
0
4
4
1.2
45
8
6
10000
10000
µs
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 9:
The absolute voltage at CHx
+
and CHx
–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17:
The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
235114f
LTC2351-14
TYPICAL PERFOR A CE CHARACTERISTICS
SINAD vs Input Frequency
77
74
THD, 2nd, 3rd (dB)
THD, 2nd, 3rd (dB)
71
SINAD (dB)
68
65
62
59
56
0.1
1
FREQUENCY (MHz)
SFDR vs Input Frequency
92
86
80
MAGNITUDE (dB)
SFDR (dB)
74
68
62
56
50
0.1
SNR (dB)
1
FREQUENCY (MHz)
100kHz Bipolar Sine Wave
8192 Point FFT Plot
0
–10
DIFFERENTIAL LINEARITY (LSB)
–30
MAGNITUDE (dB)
INTEGRAL LINEARITY (LBS)
–20
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25
75
50
FREQUENCY (kHz)
100
125
235114 G07
U W
235114 G01
235114 G04
V
DD
= 3V, T
A
= 25°C
THD, 2nd and 3rd vs Input Frequency
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
10
THD, 2nd and 3rd vs Input Frequency
–50
–56
BIPOLAR SINGLE-ENDED
UNIPOLAR SINGLE-ENDED
THD
2nd
–62
–68
–74
–80
–86
–92
–98
–104
THD
2nd
3rd
3rd
–110
0.1
1
FREQUENCY (MHz)
10
235114 G02
–110
0.1
1
FREQUENCY (MHz)
10
235114 G03
SNR vs Input Frequency
77
74
71
68
65
62
59
56
0.1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
100kHz Unipolar Sine Wave
8192 Point FFT Plot
10
1
FREQUENCY (MHz)
10
235114 G05
0
25
75
50
FREQUENCY (kHz)
100
125
235114 G06
Differential Linearity vs Output Code,
Unipolar Mode
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
4096
8192
12288
OUTPUT CODE
16384
235114 G08
Integral Linearity vs Output Code,
Unipolar Mode
4
3
2
1
0
–1
–2
–3
–4
0
4096
8192
OUTPUT CODE
235114 G09
12288
16384
235114f
5
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