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74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Rev. 8 — 28 June 2013
Product data sheet
1. General description
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features an output
enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
CC
= 0 V
Bus hold on all data inputs (74LVCH245A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC245AD
74LVCH245AD
74LVC245ADB
74LVCH245ADB
74LVC245APW
74LVCH245APW
74LVC245ABQ
74LVCH245ABQ
74LVC245ABX
74LVCH245ABX
40 C
to +125
C
DHXQFN20
40 C
to +125
C
DHVQFN20
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
40 C
to +125
C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; body 4.5
2.5
0.5 mm
SOT1045-2
4. Functional diagram
DIR
OE
2
A0
B0
3
A1
B1
4
A2
B2
5
A3
B3
6
A4
B4
7
A5
4
B5
8
A6
6
B6
9
A7
8
B7
11
9
mna175
1
19
18
17
19
16
1
G3
3EN1
3EN2
15
2
14
3
1
2
18
17
16
15
14
13
12
11
13
5
12
7
mna174
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
© NXP B.V. 2013. All rights reserved.
74LVC_LVCH245A
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 8 — 28 June 2013
2 of 18
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVC245A
74LVCH245A
terminal 1
index area
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
GND
(1)
GND 10
B7 11
13 B5
12 B6
DIR
2
3
4
5
6
7
8
9
1
A0
A1
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
001aak292
74LVC245A
74LVCH245A
A2
A3
A4
A5
A6
A7
GND 10
001aak293
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration for SO20 and (T)SSOP20
Fig 4.
Pin configuration for DHVQFN20 and
DHXQFN20
5.2 Pin description
Table 2.
Symbol
DIR
A0 to A7
GND
B0 to B7
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
direction control
data input/output
ground (0 V)
data input/output
output enable input (active LOW)
supply voltage
74LVC_LVCH245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 28 June 2013
3 of 18
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
6. Functional description
Table 3.
Inputs
OE
L
L
H
[1]
Function selection
[1]
Inputs/outputs
DIR
L
H
X
An
An = Bn
inputs
Z
Bn
inputs
Bn = An
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20 packages: above 60
C
derate linearly with 4.5 mW/K.
74LVC_LVCH245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 28 June 2013
4 of 18
嵌入式系统
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