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74LCX16652CW

产品描述Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS
产品类别逻辑    逻辑   
文件大小92KB,共10页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
下载文档 详细参数 全文预览

74LCX16652CW概述

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS

74LCX16652CW规格参数

参数名称属性值
厂商名称Fairchild
包装说明DIE,
Reach Compliance Codeunknown
系列LVC/LCX/Z
JESD-30 代码X-XUUC-N56
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
位数8
功能数量2
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料UNSPECIFIED
封装代码DIE
封装形状UNSPECIFIED
封装形式UNCASED CHIP
传播延迟(tpd)7.4 ns
认证状态Not Qualified
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式NO LEAD
端子位置UPPER
Base Number Matches1

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74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
February 1994
Revised April 1999
74LCX16652
Low Voltage Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX16652 contains sixteen non-inverting bidirectional
bus transceivers with 3-STATE outputs providing multi-
plexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Output Enable pins (OEAB, OEBA)
are provided to control the transceiver function (see Func-
tional Description).
The LCX16652 is designed for low-voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
5.7 ns t
PD
max (V
CC
=
3.3V), 20
µA
I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±24
mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74LCX16652MEA
74LCX16652MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
A
0
–A
15
B
0
–B
15
CPAB
n
, CPBA
n
SAB
n
, SBA
n
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
OEAB
n
, OEBA
n
Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation
DS012005.prf
www.fairchildsemi.com

 
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