74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver
September 2001
Revised September 2001
74ALVCH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold
General Description
The ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH16240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.
The 74ALVCH16240 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
t
PD
3.9 ns max for 3.0V to 3.6V V
CC
5.3 ns max for 2.3V to 2.7V V
CC
6.0 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Order Number
74ALVCH16240MTD
Package
Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500629
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74ALVCH16240
Connection Diagram
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
I
12
–I
15
L
H
X
I
8
–I
11
L
H
X
I
4
–I
7
L
H
X
Outputs
O
8
–O
11
H
L
Z
Outputs
O
12
–O
15
H
L
Z
I
0
–I
3
L
H
X
Outputs
O
4
–O
7
H
L
Z
Outputs
O
0
–O
3
H
L
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
Functional Description
The 74ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
trolled by an Output Enable (OE
n
) input. When OE
n
is
LOW, the outputs are in the 2-state mode. When OE
n
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
Logic Diagram
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2
74ALVCH16240
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 2)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 3)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 2:
I
O
Absolute Maximum Rating must be observed, limited to 4.6V.
Note 3:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12 mA
I
OL
=
24 mA
I
OH
High Level Output Current
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
1.65
2.3
2.7
3.0
I
OL
LOW Level Output Current
1.65
2.3
2.7
3
I
I
I
I(HOLD)
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
0
≤
V
I
≤
3.6V
V
IN
=
0.58V
V
IN
=
1.07V
V
IN
=
0.7V
V
IN
=
1.7V
V
IN
=
0.8V
V
IN
=
2.0V
0
<
V
O
≤
3.6V
3.6
1.65
1.65
2.3
2.3
3.0
3.0
3.6
25
−25
45
−45
75
−75
±500
µA
V
CC
- 0.2
1.2
2.0
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
−4
−12
−12
−24
4
12
12
24
±5.0
µA
mA
mA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVCH16240
DC Electrical Characteristics
Symbol
I
OZ
I
CC
∆I
CC
Parameter
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
3.6
3.6
3 - 3.6
Conditions
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
Min
Max
±10
40
750
Units
µA
µA
µA
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Propagation Delay
Output Enable Time
Output Disable Time
1.0
1.0
1.0
Max
3.9
5
4.4
V
CC
=
2.7V
Min
Max
5.3
6.1
4.8
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
1.0
1.0
1.0
Max
5.3
6.4
5.4
V
CC
=
1.8V
±
0.15V
Min
1.5
1.5
1.5
Max
6.0
8.2
6.8
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
Control
Data
Conditions
V
I
=
0V or V
CC
V
I
=
0V or V
CC
V
I
=
0V or V
CC
Outputs Enabled f
=
10 MHz, C
L
=
50 pF
Outputs Disabled f
=
10 MHz, C
L
=
50 pF
T
A
= +25°C
V
CC
3.3
3.3
3.3
3.3
2.5
3.3
2.5
Typical
3
6
7
19
16
5
4
pF
pF
pF
Units
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4
74ALVCH16240
AC Loading and Waveforms
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
6V at V
CC
=
3.3
±
0.3V;
V
CC
x 2 at V
CC
=
2.5
±
0.2V; 1.8V
±
0.15V
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
V
mi
V
mo
V
X
V
Y
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
5
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