S i531 6
P
RECISION
C
LOCK
J
ITTER
A
TTENUATOR
Features
Fixed frequency jitter attenuator
with selectable clock ranges at
19, 38, 77, 155, 311, and
622 MHz (710 MHz max)
Support for SONET, 10GbE,
10GFC, and corresponding FEC
rates
Ultra-low jitter clock output with
jitter generation as low as
0.3 ps
RMS
(50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(100 Hz–7.9 kHz)
Meets OC-192 GR-253-CORE
jitter specifications
Dual clock inputs with integrated
clock select mux
One clock input can be 1x, 4x, or
32x the frequency of the second
clock input
Single clock output with
selectable signal format:
LVPECL, LVDS, CML, CMOS
LOL, LOS alarm outputs
Pin programmable settings
On-chip voltage regulator for 1.8
±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size (6 x 6 mm 36-lead
QFN)
Pb-free, RoHS compliant
Ordering Information:
See page 20.
Pin Assignments
Si5316
Applications
Optical modules
SONET/SDH OC-48/OC-192/
STM-16/STM-64 line cards
10GbE, 10GFC line cards
ITU G.709 line cards
Wireless basestations
Test and measurement
Synchronous Ethernet
Description
The Si5316 is a low jitter, precision jitter attenuator for high-speed
communication systems, including OC-48, OC-192, 10G Ethernet, and
10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38,
77, 155, 311, or 622 MHz frequency range and generates a jitter-
attenuated clock output at the same frequency. Within each of these clock
ranges, the device can be tuned approximately 15% higher than nominal
SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz
range. The Si5316 is based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides any-frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is
digitally programmable, providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the
Si5316 is ideal for providing jitter attenuation in high performance timing
applications.
Patents pending
Rev. 1.0 7/12
Copyright © 2012 by Silicon Laboratories
Si5316
Si5316
Functional Block Diagram
2
Rev. 1.0
Si5316
T
A B L E O F
C
O N T E N T S
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3. Typical Applications Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5. Pin Descriptions: Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Package Outline: 36-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9.1. Si5316 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 1.0
3
Si5316
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
ºC
V
V
V
3.3 V nominal
2.5 V nominal
1.8 V nominal
2.97
2.25
1.71
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Supply Current
(Supply current is indepen-
dent of V
DD
)
CKIN Input Pins
Input Common Mode
Voltage
(Input Threshold Voltage)
Input Resistance
Input Voltage Level Limits
Single-ended Input Voltage
Swing
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
CMOS Format
19.44 MHz Out
Min
—
—
Typ
217
194
Max
243
220
Units
mA
mA
V
ICM
1.8 V ±5%
2.5 V ±10%
3.3 V ±10%
0.9
1.0
1.1
20
0
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
—
1.4
1.7
1.95
60
V
DD
—
—
—
—
V
V
V
k
V
V
PP
V
PP
V
PP
V
PP
CKN
RIN
CKN
VIN
V
ISE
Single-ended
See note
2
f
CKIN
< 212.5 MHz
See Figure 6.
f
CKIN
> 212.5 MHz
See Figure 6.
Differential Input
Voltage Swing
V
ID
f
CKIN
< 212.5 MHz
See Figure 6.
f
CKIN
> 212.5 MHz
See Figure 6.
Notes:
1.
LVPECL outputs require nominal V
DD
> 2.5 V.
2.
No overshoot or undershoot.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most
designs, an external resistor voltage divider is recommended.
4
Rev. 1.0
Si5316
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Output Clock (CKOUT)
1
Common Mode
Differential Output Swing
Single-ended Output Swing
Differential Output Voltage
Common Mode
Output Voltage
Differential
Output Voltage
Symbol
Test Condition
Min
Typ
Max
Units
CKO
VCM
CKO
VD
CKO
VSE
CKO
VD
CKO
VCM
CKO
VD
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load
line-to-line
CML 100
load
line-to-line
LVDS 100
load
line-to-line
Low swing LVDS 100
load
line-to-line
V
DD
–
1.42
1.1
0.5
350
—
500
350
1.125
—
—
0.8 x V
DD
—
—
—
425
V
DD
–
0.36
700
425
1.2
200
—
—
V
DD
–
1.25
1.9
0.93
500
—
900
500
1.275
—
0.4
—
V
V
PP
V
PP
mV
PP
V
mV
PP
mV
PP
V
V
V
Common Mode
Output Voltage
Differential Output
Resistance
Output Voltage Low
Output Voltage High
Output Drive Current
CKO
VCM
CKO
RD
CKO
VOLLH
CKO
VOHLH
CKO
IO
LVDS 100
load
line-to-line
CML, LVDS, LVPECL
CMOS
V
DD
= 1.71 V
CMOS
CMOS
Driving into CKO
VOL
for out-
put low or CKO
VOH
for output
high. CKOUT+ and CKOUT–
shorted externally.
V
DD
= 1.8 V
V
DD
= 3.3 V
—
—
7.5
32
—
—
mA
mA
Notes:
1.
LVPECL outputs require nominal V
DD
> 2.5 V.
2.
No overshoot or undershoot.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most
designs, an external resistor voltage divider is recommended.
Rev. 1.0
5
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