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7054L20GI

产品描述Four-Port SRAM, 4KX8, 20ns, CMOS, PPGA108, PGA-108
产品类别存储    存储   
文件大小196KB,共11页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

7054L20GI概述

Four-Port SRAM, 4KX8, 20ns, CMOS, PPGA108, PGA-108

7054L20GI规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码PGA
包装说明PGA-108
针数108
Reach Compliance Codecompliant
ECCN代码EAR99
最长访问时间20 ns
JESD-30 代码S-PPGA-P108
JESD-609代码e0
长度30.48 mm
内存密度32768 bit
内存集成电路类型FOUR-PORT SRAM
内存宽度8
功能数量1
端子数量108
字数4096 words
字数代码4000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织4KX8
封装主体材料PLASTIC/EPOXY
封装代码PGA
封装形状SQUARE
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)225
认证状态Not Qualified
座面最大高度5.207 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级INDUSTRIAL
端子面层TIN LEAD
端子形式PIN/PEG
端子节距2.54 mm
端子位置PERPENDICULAR
处于峰值回流温度下的最长时间20
宽度30.48 mm
Base Number Matches1

文档预览

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HIGH-SPEED
4K x 8 FourPort
TM
STATIC RAM
Features
IDT7054S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Commercial: 20/25/35ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT7054S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7054L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
P1, P2, P3, and P4
TTL-compatible; single 5V (±10%) power supply
Available in 128 pin Thin Quad Flatpack package
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Description
The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7054 is also designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to
externally arbitrated or withstand contention when all ports simulta-
neously access the same FourPort RAM location.
The IDT7054 provides four independent ports with separate control,
Functional Block Diagram
R/
W
P1
CE
P1
OE
P1
CE
P4
R/
W
P4
OE
P4
I/O
0P1
-I/O
7P1
COLUMN
I/O
COLUMN
I/O
I/O
0P4
-I/O
7P4
A
0P1
- A
11P1
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
A
0P4
- A
11P4
A
0P2
- A
11P2
A
0P3
- A
11P3
I/O
0P2
-I/O
7P2
OE
P2
CE
P2
R/
W
P2
COLUMN
I/O
COLUMN
I/O
I/O
0P3
-I/O
7P3
OE
P3
CE
P3
R/
W
P3
3241 drw 01
JULY 2018
1
©2018 Integrated Device Technology, Inc.
DSC 3241/14
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