3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
Features
Description
IDT71V424S
IDT71V424L
◆
◆
◆
◆
◆
◆
◆
◆
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
Functional Block Diagram
A
0
A
18
•
•
•
ADDRESS
DECODER
•
•
•
4,194,304-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
I/O CONTROL
8
8
WE
OE
CS
CONTROL
LOGIC
3622 drw 01
SEPTEMBER 2013
1
©2013
Integrated Device Technology, Inc.
DSC-3622/10
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
V
DD
V
SS
I/O 2
I/O 3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
I/O 4
A14
A13
A12
A11
A10
NC
3622 drw 02
Pin Configuration
NC
NC
A0
A1
A2
A3
A4
CS
I/00
I/01
V
DD
V
SS
I/02
I/03
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/07
I/06
V
SS
V
DD
I/05
I/04
A14
A13
A12
A11
A10
NC
NC
NC
SO36-1
SOJ
Top View
TSOP
Top View
Pin Description
A
0
– A
18
CS
WE
OE
I/O
0
- I/O
7
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
I/O
Power
Gnd
3622 tbl 02
3622 drw 11
Capacitance
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
8
Unit
pF
pF
3622 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Truth Table
(1,2)
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Output Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
3622 tbl 01
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
DD
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
6.42
2
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
, V
OUT
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage Relative to
V
SS
Terminal Voltage Relative
to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +4.6
-0.5 to V
DD
+0.5
-55 to +125
-55 to +125
1
50
Unit
V
V
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
0V
0V
V
DD
See Below
See Below
3622 tbl 05
C
C
W
mA
3622 tbl 04
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(2)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3
(1)
0.8
Unit
V
V
V
V
3622 tbl 06
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
NOTES:
1. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
2. V
IL
(min.) = –2V for pulse width less than 5ns, once per cycle.
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V424
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= -4mA, V
DD
= Min.
Min.
___
___
___
DC Electrical Characteristics
Max. Unit
5
5
0.4
___
µA
µA
V
V
3622 tbl 07
2.4
DC Electrical Characteristics
(1, 2, 3)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
< V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Dynamic Standby Power Supply Current
CS
> V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Full Standby Power Supply Current (static)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
L
S
L
S
L
71V424S/L 10
Com'l.
180
165
60
55
20
10
Ind.
180
165
60
55
20
10
71V424S/L 12
Com'l.
170
155
55
50
20
10
Ind.
170
155
55
50
20
10
71V424S/L 15
Com'l.
160
145
50
45
20
10
Ind.
160
145
50
45
20
10
Unit
mA
mA
mA
mA
mA
mA
3622 tbl 08
I
SB
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
- 0.2V (High).
3. Power specifications are preliminary.
4. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
6.42
3
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3622 tbl 09
AC Test Loads
+1.5V
50Ω
I/O
Z
0
= 50Ω
30pF
3622 drw 03
3.3V
320Ω
DATA
OUT
5pF*
350Ω
3622 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
•
6
Δt
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
•
•
•
•
•
•
8 20
40
60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
3622 drw 05
6.42
4
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
71V424S/L10
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
Write Enable to Output in High-Z
10
8
8
0
8
0
6
0
3
____
____
____
____
____
____
____
____
____
____
71V424S/L12
Min.
Max.
71V424S/L15
Min.
Max.
Unit
Parameter
Min.
Max.
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
10
____
____
____
12
____
____
____
15
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
4
____
____
4
____
____
4
____
____
5
5
____
6
6
____
7
7
____
0
____
0
____
0
____
5
____
____
6
____
____
7
____
____
4
0
____
4
0
____
4
0
____
10
12
15
12
8
8
0
8
0
6
0
3
____
____
____
____
____
____
____
____
____
____
15
10
10
0
10
0
7
0
3
____
____
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3622 tbl 10
6
7
7
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
5
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