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74F283 4-Bit Binary Full Adder with Fast Carry
April 1988
Revised January 2004
74F283
4-Bit Binary Full Adder with Fast Carry
General Description
The 74F283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A
0
–A
3
,
B
0
–B
3
) and a Carry input (C
0
). It generates the binary Sum
outputs (S
0
–S
3
) and the Carry output (C
4
) from the most
significant bit. The 74F283 will operate with either active
HIGH or active LOW operands (positive or negative logic).
Ordering Code:
Order Number
74F283SC
74F283PC
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Logic Symbols
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
A
0
–A
3
B
0
–B
3
C
0
S
0
–S
3
C
4
Description
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
U.L.
Input I
IH
/I
IL
20
µ
A/
−
1.2 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
0.6 mA
HIGH/LOW Output I
OH
/I
OL
1.0/2.0
1.0/2.0
1.0/1.0
50/33.3
50/33.3
−
1 mA/20 mA
−
1 mA/20 mA
© 2004 Fairchild Semiconductor Corporation
DS009513
www.fairchildsemi.com
74F283
Functional Description
The 74F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
0
). The binary sum appears on the Sum
(S
0
–S
3
) and outgoing carry (C
4
) outputs. The binary weight
of the various inputs and outputs is indicated by the sub-
script numbers, representing powers of two.
2
0
(A
0
+
B
0
+
C
0
)
+
2
1
(A
1
+
B
1
)
However, other means can be used to effectively insert a
carry into, or bring a carry out from, an intermediate stage.
Figure 2 shows how to make a 3-bit adder. Tying the oper-
and inputs of the fourth adder (A
3
, B
3
) LOW makes S
3
dependent only on, and equal to, the carry from the third
adder. Using somewhat the same principle, Figure 3 shows
a way of dividing the 74F283 into a 2-bit and a 1-bit adder.
The third stage adder (A
2
, B
2
, S
2
) is used merely as a
means of getting a carry (C
10
) signal into the fourth stage
(via A
2
and B
2
) and bringing out the carry from the second
stage on S
2
. Note that as long as A
2
and B
2
are the same,
whether HIGH or LOW, they do not influence S
2
. Similarly,
when A
2
and B
2
are the same the carry into the third stage
does not influence the carry out of the third stage. Figure 4
shows a method of implementing a 5-input encoder, where
the inputs are equally weighted. The outputs S
0
, S
1
and S
2
present a binary number equal to the number of inputs I
1
–
I
5
that are true. Figure 5 shows one method of implement-
ing a 5-input majority gate. When three or more of the
inputs I
1
–I
5
are true, the output M
5
is true.
+
2
2
(A
2
+
B
2
)
+
2
3
(A
3
+
B
3
)
=
S
0
+
2S
1
+
4S
2
+
8S
3
+
16C
4
Where (
+
)
=
plus
Interchanging inputs of equal weight does not affect the
operation. Thus C
0
, A
0
, B
0
can be arbitrarily assigned to
pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier
packages. Due to the symmetry of the binary add function,
the 74F283 can be used either with all inputs and outputs
active HIGH (positive logic) or with all inputs and outputs
active LOW (negative logic). See Figure 1. Note that if C
0
is
not used it must be tied LOW for active HIGH logic or tied
HIGH for active LOW logic.
Due to pin limitations, the intermediate carries of the
74F283 are not brought out for use as inputs or outputs.
C
0
Logic Levels
Active HIGH
Active LOW
Active HIGH: 0
+
10
+
9
=
3
+
16
A
0
L
0
1
A
1
H
1
0
A
2
L
0
1
A
3
H
1
0
B
0
H
1
0
B
1
L
0
1
B
2
L
0
1
B
3
H
1
0
S
0
H
1
0
S
1
H
1
0
S
2
L
0
1
S
3
L
0
1
C
4
H
1
0
L
0
1
Active LOW: 1
+
5
+
6
=
12
+
0
FIGURE 1. Active HIGH versus Active LOW Interpretation
FIGURE 2. 3-Bit Adder
FIGURE 3. 2-Bit and 1-Bit Adders
FIGURE 4. 5-Input Encoder
FIGURE 5. 5-Input Majority Gate
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2
74F283
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F283
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
36
36
4.75
3.75
−0.6
−1.2
−150
55
55
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (C
O
)
V
IN
=
0.5V (A
n
, B
n
)
V
OUT
=
0V
V
O
=
HIGH
V
O
=
LOW
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
C
0
to S
n
Propagation Delay
A
n
or B
n
to S
n
Propagation Delay
C
0
to C
4
Propagation Delay
A
n
or B
n
to C
4
3.5
3.0
3.0
3.0
3.0
3.0
3.0
2.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
7.0
7.0
7.0
7.0
5.7
5.4
5.7
5.3
Max
9.5
9.5
9.5
9.5
7.5
7.0
7.5
7.0
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
C
L
=
50 pF
Min
3.5
3.0
3.0
3.0
3.0
2.5
3.0
2.5
Max
14.0
14.0
17.0
14.0
10.5
10.0
10.5
10.0
T
A
=
0°C to
+70°C
V
CC
=
5.0V
C
L
=
50 pF
Min
3.5
3.0
3.0
3.0
3.0
3.0
3.0
2.5
Max
11.0
11.0
13.0
11.5
8.5
8.0
8.5
8.0
ns
ns
ns
ns
Units
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4
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