3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
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71V124SA
Features
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128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15ns
– Industrial: 10/12/15ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs. The JEDEC center power/GND pinout reduces noise
generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns available. All bidirectional
inputs and outputs of the IDT71V124 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used;
no clocks or refreshes are required for operation.
Description
Functional Block Diagram
A
0
•
•
•
A
16
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
8
I/O CONTROL
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
1
Jun.30.20
71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Pin Configurations
(1)
A
0
A
1
A
2
A
3
CS
I/O
0
I/O
1
V
DD
GND
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
71V124 28
PJG32 27
PBG32 26
PHG32 25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
GND
V
DD
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
, V
OUT
Rating
Supply Voltage Relative
to GND
Terminal Voltage Relative
to GND
Commercial
Operating Temperature
Industrial
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +4.6
-0.5 to V
DD
+0.5
-0 to +70
o
Unit
V
V
T
A
C
-40 to +85
-55 to +125
-55 to +125
1.25
50
o
o
T
BIAS
T
STG
P
T
I
OUT
C
C
W
mA
3873 drw 02
SOJ and TSOP
Top View
NOTE:
1. This text does not indicate oriebtation of actual part-marking.
3873 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Truth Table
(1)
CS
L
L
L
H
OE
L
X
H
X
WE
H
L
H
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
Read Data
Write Data
Output Disabled
Deselected – Standby
3873 tbl 01
Function
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
GND
0V
0V
V
DD
See Below
See Below
3873 tb l 02a
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.15
3.0
0
2.0
–0.5
(1)
Typ.
3.3
3.3
0
____
____
Max.
3.6
3.6
0
V
DD
+0.3
(3)
0.8
Unit
V
V
V
V
V
3873 tbl 04
Capacitance
Symbol
C
IN
C
I/O
V
DD
(1)
V
DD
(2)
Unit
pF
pF
3873 tbl 03
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
V
SS
V
IH
V
IL
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
DC Electrical Characteristics
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
NOTES:
1. For 71V124SA10 only.
2. For all speed grades except 71V124SA10.
3. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
4. V
IL
(min.) = –2V for pulse width less than 5ns, once per cycle.
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
Test Conditions
V
DD
= Max., V
IN =
GND to V
DD
V
DD
= Max.,CS
=
V
IH
, V
OUT =
GND to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= –4mA, V
DD
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3873 tbl 05
2.4
2
Jun.30.20
71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(1, 2)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
71V124SA10
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
CS
< V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Dynamic Standby Power Supply Current
CS
> V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Full Standby Power Supply Current (static)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
Commercial
145
45
10
71V124SA12
Com'l
130
40
10
Ind
140
40
10
71V124SA15
Com'l
100
35
10
Ind
120
40
10
Unit
mA
mA
mA
3873 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
–0.2V (High).
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3873 tbl 07
3.3V
320Ω
DATA
OUT
5pF*
30pF
3873 drw 03
+1.5V
50Ω
I/O
Z
0
= 50Ω
350Ω
3873 drw 04
.
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
3
6.42
Jun.30.20
71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
71V124SA10
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
10
____
____
____
71V124SA12
Min.
Max.
71V124SA15
Min.
Max.
Unit
Parameter
Min.
Max.
12
____
____
____
15
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
4
0
____
4
0
____
4
0
____
5
5
____
6
6
____
7
7
____
0
0
4
0
0
4
0
0
4
5
____
5
____
5
____
WRITE CYCLE
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(2)
t
WHZ
(2)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Active from End-of-Write
Write Enable to Output in High-Z
10
7
7
0
7
0
5
0
3
0
____
____
____
____
____
____
____
____
____
12
8
8
0
8
0
6
0
3
0
____
____
____
____
____
____
____
____
____
15
10
10
0
10
0
7
0
3
0
____
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3873 tbl 08
5
5
5
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
4
Jun.30.20
71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ (5)
t
ACS(3)
t
CLZ(5)
HIGH IMPEDANCE
DATA
OUT
DATA
OUT
VALID
3873 drw 05
t
OHZ (5)
t
CHZ (5)
.
Timing Waveform of Read Cycle No. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3873 drw 06
.
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
5
6.42
Jun.30.20
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