HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
◆
70V35/34S/L
70V25/24S/L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35
– Commercial: 15ns (max.)
– Industrial: 20ns
IDT70V34
– Commercial: 15ns (max.)
IDT70V25
– Commercial: 15/35ns (max.)
– Industrial: 20/25ns
IDT70V24
– Commercial: 15//35/55ns (max.)
– Industrial: 15/20ns
Low-power operation
– IDT70V35/34L
Active: 415mW (typ.)
Standby: 660
μ
W (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
– IDT70V25/24S
– IDT70V25/24L
Active: 400mW (typ.)
Active: 380mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
μ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24),
and 84-pin PLCC (IDT70V24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/W
R
UB
R
Functional Block Diagram
R/W
L
UB
L
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
Control
I/O
0L
-I/O
8L
(4)
BUSY
L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
A
12R
(1)
A
0R
A
12L
(1)
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
INT
L
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70V25/24.
5. I/O
8
x - I/O
15
x for IDT70V25/24.
©2019 Integrated Device Technology, Inc.
(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5624 drw 01
M/S
OCTOBER 2019
1
DSC-5624/10
70V35/34S/L (70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de-
signed to be used as a stand-alone Dual-Port RAM or as a combination
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 430mW (IDT70V35/34) and 400mW
(IDT70V25/24) of power.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
Thin Quad Flatpack. The IDT70V24 is packaged in a 84-Pin PLCC.
Pin Configurations
(1,2,3,4)
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
Vss
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
49
77
48
78
47
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
(1)
LB
L
UB
L
CE
L
SEM
L
R/W
L
V
DD
OE
L
I/O
0L
I/O
1L
Vss
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
9L
I/O
10L
70V35/34
PNG100
(5)
100-Pin TQFP
Top View
28
99
27
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
(1)
LB
R
UB
R
CE
R
SEM
R
Vss
R/W
R
OE
R
I/O
16R
Vss
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
I/O
9R
I/O
7R
5624 drw 02
NOTES:
1. A
12
is a NC for IDT70V34.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PNG100 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
Vss
I/O
15L
I/O
16L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
6.42
2
70V35/34S/L (70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't)
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
(1)
LB
L
UB
L
CE
L
SEM
L
R/W
L
V
DD
OE
L
I/O
0L
I/O
1L
V
SS
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
I/O
9L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2
3
4
5
6
7
8
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
70V25/24
PNG100
(5)
100-Pin TQFP
Top View
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
(1)
LB
R
UB
R
CE
R
SEM
R
V
SS
R/W
R
OE
R
I/O
15R
V
SS
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
I/O
9R
I/O
8R
I/O
7R
5624 drw 03
NOTES:
1. A
12
is a NC for IDT70V24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PNG100 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
V
SS
I/O
14L
I/O
15L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
6.42
3
70V35/34S/L (70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't)
I/O
8R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
V
SS
V
DD
I/O
15L
I/O
14L
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
V
SS
I/O
15R
OE
R
R/W
R
V
SS
SEM
R
CE
R
UB
R
LB
R
A
12R
(1)
A
11R
A
10R
A
9R
A
8R
A
7R
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
33
11
34
10
35
9
36
8
37
7
38
6
39
5
40
4
41
3
42
70V24
2
PLG84
(5)
43
1
44
84-Pin PLCC
84
Top View
45
83
46
82
47
81
48
80
49
79
50
78
51
77
52
76
53
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
V
SS
I/O
13L
I/O
12L
I/O
11L
I/O
10L
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
(1)
A
11L
A
10L
A
9L
A
8L
A
0R
INT
R
A
6R
A
4R
A
3R
A
2R
A
1R
BUSY
R
INT
L
A
5R
BUSY
L
M/S
V
SS
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
5624 drw 05
NOTES:
1. A
12
is a NC for IDT70V24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PLG84 package body is approximately 1.15 in x 1.15 in x .17 in.
5. This package code is used to reference the package diagram.
6.42
4
70V35/34S/L (70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
(1)
I/O
0L
- I/O
17L
(2)
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
12R
(1)
I/O
0R
- I/O
17R
(2)
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
DD
V
SS
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
(3)
Lower Byte Select
(4)
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3V)
Ground (0V)
5624 tbl 01
Names
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. I/O
0
x - I/O
15
x for IDT70V25/24.
3. Upper Byte Select controls pins 9-17 for IDT70V35/34 and controls pins 8-15
for IDT70V25/24.
4. Lower Byte Select controls pins 0-8 for IDT70V35/34 and controls pins 0-7
for IDT70V25/24.
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
9-17
(3)
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Outputs
I/O
0-8
(2)
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
5624 tbl 02
Mode
NOTES:
1. A
0L
-A
12L
≠
A
0R
-A
12R
for IDT70V35/34 and A
0L
-A
11L
≠
A
0R
-A
11R
for IDT70V25/24.
2. Outputs listed in the table are for IDT70V35/34. Outputs for IDT70V25/24 are I/O
0
x-I/O
7
x.
3. Outputs listed in the table are for IDT70V35/34. Outputs for IDT70V25/24 are I/O
8
x-I/O
15
x.
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
X
H
X
L
L
R/W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
9-17
(1)
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Outputs
I/O
0-8
(1)
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
5624 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
-I/O
17
for IDT70V35/34) and (I/O
0
-I/O
15
for IDT70V25/24). These eight semaphores
are addressed by A
0
-A
2
.
6.42
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
