Hitachi Single-Chip Microcomputer
H8/3217 Series
H8/3217, H8/3216
H8/3214, H8/3212
H8/3202
Hardware Manual
29.08.1996
Notice
When using this document, keep the following in mind:
1.
2.
3.
4.
This document may, wholly or partially, be subject to change without notice.
All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole
or part of this document without Hitachi’s permission.
Hitachi will not be held responsible for any damage to the user that may result from accidents
or any other reasons during operation of the user’s unit according to this document.
Circuitry and other examples described herein are meant merely to indicate the characteristics
and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for
any intellectual property claims or other problems that may result from applications based on
the examples described herein.
No license is granted by implication or otherwise under any patents or other rights of any third
party or Hitachi, Ltd.
MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
5.
6.
Preface
The H8/3217 Series is a family of high-performance single-chip microcomputers ideally suited for
embedded control of industrial equipment. The chips are built around an H8/300 CPU core: a high-speed
processor. On-chip supporting modules provide ROM, RAM, four types of timers, I/O ports, a serial
communication interface, I
2
C bus interface, and host interface for easy implementation of compact, high-
speed control systems.
The H8/3217 Series offers a selection of on-chip memory.
H8/3217:
H8/3216:
H8/3214:
H8/3212:
60-kbyte ROM;
48-kbyte ROM;
32-kbyte ROM;
16-kbyte ROM;
2-kbyte RAM
2-kbyte RAM
1-kbyte RAM
512-byte RAM
The H8/3217 and H8/3214 chips are available with electrically programmable ROM. Manufacturers can use
the electrically programmable ZTAT™ (Zero Turn-Around Time*) version to get production off to a fast
start and make software changes quickly.
This manual describes the H8/3217 Series hardware. Refer to the
H8/300 Series Programming Manual
for a
detailed description of the instruction set.
Note:
* ZTAT is a trademark of Hitachi, Ltd.
Contents
Section 1 Overview
.............................................................................................................
1.1
1.2
1.3
Overview...........................................................................................................................
Block Diagram..................................................................................................................
Pin Assignments and Functions........................................................................................
1.3.1 Pin Arrangement .................................................................................................
1.3.2 Pin Functions .......................................................................................................
1
1
6
7
7
10
Section 2 CPU
...................................................................................................................... 25
2.1
Overview...........................................................................................................................
2.1.1 Features ...............................................................................................................
2.1.2 Address Space .....................................................................................................
2.1.3 Register Configuration ........................................................................................
Register Descriptions........................................................................................................
2.2.1 General Registers.................................................................................................
2.2.2 Control Registers .................................................................................................
2.2.3 Initial Register Values .........................................................................................
Data Formats.....................................................................................................................
2.3.1 Data Formats in General Registers......................................................................
2.3.2 Memory Data Formats.........................................................................................
Addressing Modes ............................................................................................................
2.4.1 Addressing Modes ...............................................................................................
2.4.2 Effective Address Calculation .............................................................................
Instruction Set ...................................................................................................................
2.5.1 Data Transfer Instructions ...................................................................................
2.5.2 Arithmetic Operations .........................................................................................
2.5.3 Logic Operations .................................................................................................
2.5.4 Shift Operations ...................................................................................................
2.5.5 Bit Manipulations ................................................................................................
2.5.6 Branching Instructions.........................................................................................
2.5.7 System Control Instructions ................................................................................
2.5.8 Block Data Transfer Instruction ..........................................................................
CPU States ........................................................................................................................
2.6.1 Program Execution State .....................................................................................
2.6.2 Exception-Handling State ...................................................................................
2.6.3 Power-Down State ...............................................................................................
Access Timing and Bus Cycle..........................................................................................
2.7.1 Access to On-Chip Memory (RAM and ROM) ..................................................
2.7.2 Access to On-Chip Register Field and External Devices ....................................
25
25
26
26
27
27
27
28
29
30
31
32
32
33
37
39
41
42
42
44
49
51
52
54
55
55
56
56
56
59
2.2
2.3
2.4
2.5
2.6
2.7
Section 3 MCU Operating Modes and Address Space
............................................ 63
3.1
3.2
3.3
3.4
3.5
Overview ..........................................................................................................................
3.1.1 Operating Modes ................................................................................................
3.1.2 Mode and System Control Registers ..................................................................
System Control Register (SYSCR) ..................................................................................
Mode Control Register (MDCR) .....................................................................................
Mode Descriptions ...........................................................................................................
Address Space Maps for Each Operating Mode ..............................................................
63
63
63
64
66
66
67
Section 4 Exception Handling
........................................................................................ 73
4.1
4.2
Overview ..........................................................................................................................
Reset.................................................................................................................................
4.2.1 Overview.............................................................................................................
4.2.2 Reset Sequence ...................................................................................................
4.2.3 Disabling of Interrupts after Reset ......................................................................
Interrupts ..........................................................................................................................
4.3.1 Overview.............................................................................................................
4.3.2 Interrupt-Related Registers .................................................................................
4.3.3 External Interrupts ..............................................................................................
4.3.4 Internal Interrupts................................................................................................
4.3.5 Interrupt Handling ..............................................................................................
4.3.6 Interrupt Response Time.....................................................................................
4.3.7 Precaution ...........................................................................................................
Note on Stack Handling ...................................................................................................
Notes on the Use of Key-Sense Interrupts .......................................................................
73
73
73
74
77
77
77
79
82
83
83
89
89
90
91
4.3
4.4
4.5
Section 5 Wait-State Controller
..................................................................................... 93
5.1
Overview ..........................................................................................................................
5.1.1 Features ...............................................................................................................
5.1.2 Block Diagram ....................................................................................................
5.1.3 Input/Output Pins ................................................................................................
5.1.4 Register Configuration ........................................................................................
Register Description.........................................................................................................
5.2.1 Wait-State Control Register (WSCR).................................................................
Wait Modes ......................................................................................................................
93
93
93
94
94
94
94
96
5.2
5.3
Section 6 Clock Pulse Generator
................................................................................... 99
6.1
Overview ..........................................................................................................................
6.1.1 Block Diagram ....................................................................................................
6.1.2 Wait-State Control Register (WSCR).................................................................
Oscillator Circuit ..............................................................................................................
Duty Adjustment Circuit ..................................................................................................
Prescaler ...........................................................................................................................
99
99
100
101
107
107
6.2
6.3
6.4
Section 7 I/O Ports
............................................................................................................. 109
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