LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-
LVHSTL FANOUT BUFFER
ICS85211I
G
ENERAL
D
ESCRIPTION
The ICS85211I is a low skew, high performance 1-to-2
Differential-to-LVHSTL Fanout Buffer . The CLK, nCLK pair
can accept most standard differential input levels.T h e
ICS85211I is characterized to operate from a 3.3V power
supply. Guaranteed output and part-to-part skew
characteristics make the ICS85211I ideal for those clock
distribution applications demanding well defined
performance and repeatability. For optimal performance,
terminate all outputs.
F
EATURES
•
Two differential LVHSTL compatible outputs
•
One differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 700MHz
•
Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1ns (maximum)
•
Output duty cycle: 49% - 51% up to 266.6MHz
•
V
OH
= 1.2V (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK
nCLK
GND
CLK
nCLK
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
ICS85211I
IDT
™
/ ICS
™
1-TO-2 LVHSTL FANOUT BUFFER
1
ICS85211I REV D JULY 26, 2010
ICS85211I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
nCLK
CLK
V
DD
Type
Output
Output
Power
Input
Input
Power
V
DD
/2
Description
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
Inver ting differential clock input. V
DD
/2 default when left floating.
Positive supply pin.
Pulldown Non-inver ting differential clock input.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0, Q1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0, nQ1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
IDT
™
/ ICS
™
1-TO-2 LVHSTL FANOUT BUFFER
2
ICS85211I REV D JULY 26, 2010
ICS85211I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
DD
Outputs, V
DD
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
0.5
V
CMR
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
1.0
0
0.6
0.9
Typical
Maximum
1.2
0.4
1.2
Units
V
V
V
NOTE 1: All outputs must be terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
47
IJ 600MHz
0.7
Test Conditions
Minimum
Typical
Maximum
700
1.0
30
250
600
53
Units
MHz
ns
ps
ps
ps
%
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
1-TO-2 LVHSTL FANOUT BUFFER
3
ICS85211I REV D JULY 26, 2010
ICS85211I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V±5%
V
DD
Qx
SCOPE
V
DD
nCLK
LVHSTL
GND
nQx
V
PP
Cross Points
V
CMR
CLK
GND
0V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
Qx
nQy
Qy
tsk(o)
D
IFFERENTIAL
I
NPUT
L
EVEL
Qx
PART 1
nQx
Qy
PART 2
nQy
tsk(pp)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
nCLK
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
CLK
nQ0, nQ1
Q0, Q1
t
PD
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0, nQ1
Q0, Q1
P
ROPAGATION
D
ELAY
t
PW
t
PERIOD
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
P
ULSE
W
IDTH
/P
ERIOD
IDT
™
/ ICS
™
1-TO-2 LVHSTL FANOUT BUFFER
4
ICS85211I REV D JULY 26, 2010
ICS85211I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
A
PPLICATION
I
NFORMATION
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R
ECOMMENDATIONS FOR
U
NUSED
O
UTPUT
P
INS
O
UTPUTS
:
LVHSTL O
UTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT
™
/ ICS
™
1-TO-2 LVHSTL FANOUT BUFFER
5
ICS85211I REV D JULY 26, 2010
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