ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8524 is a low skew, 1-to-22 Differential-to-HSTL
Fanout Buffer . The ICS8524 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The device is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the OE pin. The
ICS8524’s low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high
performance clock distribution applications.
F
EATURES
•
Twenty-two differential HSTL outputs
each with the ability to drive 50Ω to ground
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 500MHz
•
Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to HSTL levels with resistor bias on nCLK input
•
Output skew: 80ps (maximum)
•
Part-to-part skew: 700ps (maximum)
•
Jitter, RMS: 0.04ps (typical)
•
LVPECL and HSTL mode operating voltage supply range: V
DD
= 3.3V ± 5%, V
DDO
= 1.6V to 2V, GND = 0V
•
0°C to 85°C ambient operating temperature
B
LOCK
D
IAGRAM
CLK_SEL
CLK
nCLK
PCLK
nPCLK
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
V
DDO
nQ13
Q13
nQ12
Q12
nQ11
Q11
nQ10
Q10
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
DDO
0
22
22
Q0:Q21
nQ0:nQ21
1
LE
Q
OE
D
V
DDO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
ICS8524
V
DDO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
DDO
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
8524AY
www.idt.com
1
V
DDO
nc
nc
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
OE
nc
nc
nQ21
Q21
V
DDO
REV. B DECEMBER 6, 2010
ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 16, 17, 32,
33, 48, 49, 64
2, 3, 12, 13
4
5
6
7
8
9
10
11
14, 15
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
50, 51
52, 53
54, 55
56, 57
58, 59
60, 61
62, 63
NOTE:
Pullup
and
Name
V
DDO
nc
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
OE
nQ21, Q21
nQ20, Q20
nQ19, Q19
nQ18, Q18
nQ17, Q17
nQ16, Q16
nQ15, Q15
nQ14, Q14
nQ13, Q13
nQ12, Q12
nQ11, Q11
nQ10, Q10
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Pulldown
refer
Power
Unused
Power
Input
Input
Input
Input
Input
Power
Input
Output
Output
Output
Output
Output
Type
Description
Output supply pins.
No connect.
Core supply pin.
Pulldown Non-inver ting differential clock input pair.
Pullup/
Inver ting differential clock input pair. Biased to
2
/
3
V
CC
.
Pulldown
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
Pullup
When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input pair.
Pullup/
Inver ting differential LVPECL clock input pair. Biased to
2
/
3
V
CC
.
Pulldown
Power supply ground.
Output enable. Controls enabling and disabling of outputs
Pullup
Q0:Q21, nQ0:nQ21. LVCMOS / LVTTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Output
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
Output
Differential clock outputs. HSTL interface levels.
to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8524AY
www.idt.com
2
REV. B DECEMBER 6, 2010
ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
37
75
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE
0
0
1
1
CLK_SEL
0
1
0
1
Outputs
Q0:Q21
nQ0:nQ21
LOW
HIGH
LOW
CLK
PCLK
HIGH
nCLK
nPCLK
nCLK,
nPCLK
CLK,PCLK
Disabled
Enabled
OE
nQ0 :nQ21
Q0 :Q21
F
IGURE
1. OE T
IMING
D
IAGRAM
8524AY
www.idt.com
3
REV. B DECEMBER 6, 2010
ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
22.3°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
No Load
1
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
220
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE, CLK_SEL
OE, CLK_SEL
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
CLK, nCLK
CLK, nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
8524AY
www.idt.com
4
REV. B DECEMBER 6, 2010
ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK, nPCLK
PCLK, nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
0.3
1
V
DD
Minimum
Typical
Maximum
150
Units
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
T
ABLE
4E. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.4
0.4
60
1.1
Units
V
V
%
V
V
SWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
=0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Setup Time
Hold Time
Output Duty Cycle
IJ 133MHz
1.7
Test Conditions
Minimum
Typical
Maximum
500
2.7
80
700
0.04
20% to 80%
300
1.0
0.5
49
51
52
700
Units
MHz
ns
ps
ps
ps
ps
ns
ns
%
%
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
t
S
t
H
odc
133 < ƒ
≤
266MHz
48
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions at the same temperature. Using the same type of inputs on each device,
the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8524AY
www.idt.com
5
REV. B DECEMBER 6, 2010
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
