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CY7C64713/14
EZ-USB FX1™ USB Microcontroller
Full-speed USB Peripheral Controller
1.0
Features
•
•
Single-chip integrated USB transceiver, SIE, and
enhanced 8051 microprocessor
•
Fit, form and function upgradable to the FX2LP
(CY7C68013A)
— Pin-compatible
— Object-code-compatible
— Functionally-compatible (FX1 functionality is a
Subset of the FX2LP)
• Draws no more than 65 mA in any mode making the FX1
suitable for bus powered applications
• Software: 8051 runs from internal RAM, which is:
— Downloaded via USB
— Loaded from EEPROM
— External memory device (128-pin configuration only)
• 16 KBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCH-
RONOUS endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF
— Allows direct connection to most parallel interfaces;
8- and 16-bit
— Programmable waveform descriptors and configu-
ration registers to define waveforms
24 MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
•
•
•
•
•
•
•
•
•
•
— Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
Integrated, industry standard 8051 with enhanced
features
— Up to 48-MHz clock rate
— Four clocks per instruction cycle
— Two USARTS
— Three counter/timers
— Expanded interrupt system
— Two data pointers
3.3V operation with 5V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the Setup and DATA portions
of a CONTROL transfer
Integrated I
2
C controller, runs at 100 or 400 KHz
48-MHz, 24-MHz, or 12-MHz 8051 operation
Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— FIFOs can use externally supplied clock or
asynchronous strobes
— Easy interface to ASIC and DSP ICs
Vectored for FIFO and GPIF interrupts
Up to 40 general purpose I/Os
Three package options—128-pin TQFP, 100-pin TQFP,
and 56-pin QFN Lead-free
Address (16)
Data (8)
FX1
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Master
Additional I/Os (24)
1.5k
connected for
enumeration
D+
USB
D–
Integrated
full-speed XCVR
XCVR
CY
Smart
USB
Engine
16 KB
RAM
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 18, 2005
CY7C64713/14
2.0
Functional Description
4.2
8051 Microprocessor
EZ-USB FX1
(CY7C64713/4) is a full-speed highly
integrated, USB microcontroller. By integrating the USB trans-
ceiver, serial interface engine (SIE), enhanced 8051 microcon-
troller, and a programmable peripheral interface in a single
chip, Cypress has created a very cost-effective solution that
provides superior time-to-market advantages.
Because it incorporates the USB transceiver, the EZ-USB FX1
is more economical, providing a smaller footprint solution than
USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application-specific functions and decreasing development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/
Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy
and glueless interface to popular interfaces such as ATA,
UTOPIA, EPP, PCMCIA, and most DSP/processors.
Three lead-free packages are defined for the family: 56 QFN,
100 TQFP, and 128 TQFP.
The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system,
three timer/counters, and two USARTs.
4.2.1
8051 Clock Frequency
3.0
•
•
•
•
•
•
•
•
Applications
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Home PNA
Wireless LAN
MP3 players
Networking
The “Reference Designs” section of the cypress website
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are
shown in
Table 4-1.
Bold type indicates non-standard,
4.1
USB Signaling Speed
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit-addressable registers. The four I/O ports
FX1 operates at one of the three rates defined in the USB
A–D use the SFR addresses used in the standard 8051 for
Specification Revision 2.0, dated April 27, 2000:
ports 0–3, which are not implemented in FX1. Because of the
• Full speed, with a signaling bit rate of 12 Mbps.
faster and more efficient SFR addressing, the FX1 I/O ports
are not addressable in external RAM space (using the MOVX
FX1 does not support the low-speed signaling mode of 1.5
instruction).
Mbps or the high-speed mode of 480 Mbps.
C1 24 MHz C2
4.0
Functional Overview
Note:
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.
Document #: 38-08039 Rev. *C
FX1 has an on-chip oscillator circuit that uses an external 24-
MHz (±100 ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
• 500-µW drive level
• 12-pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480
MHz, as required by the transceiver/PHY, and internal
counters divide it down for use as the 8051 clock. The default
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically.
The CLKOUT pin, which can be three-stated and inverted
using internal control bits, outputs the 50% duty cycle 8051
clock, at the selected 8051 clock frequency—48, 24, or 12
MHz.
4.2.2
USARTS
FX1 contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface
pins are available on separate I/O pins, and are not multi-
plexed with port pins.
UART0 and UART1 can operate using an internal clock at 230
KBaud with no more than 1% baud rate error. 230-KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The
internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)
such that it always presents the correct frequency for 230-
KBaud operation.
[1]
4.2.3
Special Function Registers
12 pF
12 pF
20 × PLL
12-pF capacitor values assumes a trace
capacitance of 3 pF per side on a four-layer FR4 PCA
Figure 4-1. Crystal Configuration
Page 2 of 50
CY7C64713/14
Table 4-1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
SCON0
SBUF0
AUTOPTRH1
AUTOPTRL1
reserved
AUTOPTRH2
AUTOPTRL2
reserved
AUTOPTRSETUP
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATLNOX
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TH2
IE
IP
T2CON
EICON
EIE
EIP
9x
IOB
EXIF
MPAGE
Ax
IOC
INT2CLR
INT4CLR
Bx
IOD
IOE
OEA
OEB
OEC
OED
OEE
Cx
SCON1
SBUF1
Dx
PSW
Ex
ACC
Fx
B
4.3
I
2
C Bus
4.6
ReNumeration™
FX1 supports the I
2
C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
2
C
device is connected.
Because the FX1’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX1 enumerates automati-
cally and downloads firmware and USB descriptor tables over
the USB cable. Next, the FX1 enumerates again, this time as
a device defined by the downloaded information. This
patented two-step process, called ReNumeration , happens
instantly when the device is plugged in, with no hint that the
initial download step has occurred.
Two control bits in the USBCS (USB Control and Status)
register control the ReNumeration process: DISCON and
RENUM. To simulate a USB disconnect, the firmware sets
DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM
bit to indicate whether the firmware or the Default USB Device
will handle device requests over endpoint zero: if RENUM = 0,
the Default USB Device will handle device requests; if RENUM
= 1, the firmware will.
4.4
Buses
All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-
plexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
4.5
USB Boot Methods
During the power-up sequence, internal logic checks the I
2
C
port for the connection of an EEPROM whose first byte is
either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values
in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM
(0xC2). If no EEPROM is detected, FX1 enumerates using
internally stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).
[2]
Table 4-2. Default ID Values for FX1
Default VID/PID/DID
Vendor ID
Device
release
0x04B4 Cypress Semiconductor
0xAnnn Depends chip revision (nnn = chip
revision where first silicon = 001)
Product ID 0x6473 EZ-USB FX1
4.7
Bus-powered Applications
The FX1 fully supports bus-powered designs by enumerating
with less than 100 mA as required by the USB specification.
4.8
4.8.1
Interrupt System
INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
Note:
2.
The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document #: 38-08039 Rev. *C
Page 3 of 50
CY7C64713/14
4.8.2
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that normally would be
required to identify the individual USB interrupt source, the
FX1 provides a second level of interrupt vectoring, called
Autovectoring. When a USB interrupt is asserted, the FX1
pushes the program counter onto its stack then jumps to
address 0x0043, where it expects to find a “jump” instruction
to the USB Interrupt service routine.
The FX1 jump instruction is encoded as shown in
Table 4-3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if
Table 4-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
INT2VEC Value
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
reserved
reserved
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP4
EP6
EP8
IBN
EP0ACK
SUDAV
SOF
SUTOK
SUSPEND
USB RESET
Source
Setup Data Available
Start of Frame
Setup Token Received
USB Suspend request
Bus reset
reserved
FX1 ACK’d the CONTROL Handshake
reserved
EP0-IN ready to be loaded with data
EP0-OUT has USB data
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
reserved
EP0 OUT was Pinged and it NAK’d
EP1 OUT was Pinged and it NAK’d
EP2 OUT was Pinged and it NAK’d
EP4 OUT was Pinged and it NAK’d
EP6 OUT was Pinged and it NAK’d
EP8 OUT was Pinged and it NAK’d
Bus errors exceeded the programmed limit
Notes
the high byte (“page”) of a jump-table address is preloaded at
location 0x0044, the automatically-inserted INT2VEC byte at
0x0045 will direct the jump to the correct address out of the 27
addresses within the page.
4.8.3
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB-
interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like
the USB Interrupt, can employ autovectoring.
Table 4-4
shows
the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
Document #: 38-08039 Rev. *C
Page 4 of 50
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