LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS
FANOUT BUFFER W/INTERNAL TERMINATION
ICS889833
G
ENERAL
D
ESCRIPTION
The ICS889833 is a high speed 1-to-4 Differential-
to-LVDS Fanout Buffer w/Internal Termination and
HiPerClockS™
is a member of the HiPerClockS™ family of high
perfor mance clock solutions from IDT. The
ICS889833 is optimized for high speed and very
low output skew, making it suitable for use in demanding
applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet,
and Fibre Channel. The internally terminated differential input
and V
REF
_
AC
pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input
with minimal use of external components. The device also has
an output enable pin which may be useful for system test and
debug purposes. The ICS889833 is packaged in a small 3mm
x 3mm 16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
F
EATURES
•
Four differential LVDS outputs
•
IN, nIN input pair can accept the following differential input
levels: LVPECL, LVDS, CML
•
Output frequency: >2GHz
•
Cycle-to-cycle jitter, RMS: 0.2ps (maximum)
•
Additive phase jitter, RMS: 0.04ps (typical)
•
Total jitter: 10ps (maximum)
•
Output skew: 40ps (maximum)
•
Part-to-part skew: 200ps (maximum)
•
Propagation delay: 520ps (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
IN
50Ω
P
IN
A
SSIGNMENT
nQ3
Q0 1
nQ0 2
Q1 3
nQ1 4
16 15 14 13
12
11
10
9
5
Q2
V
DD
Q3
GND
IN
V
T
V
REF
_
AC
nIN
Q1
nQ1
50Ω
V
T
nIN
6
nQ2
7
V
DD
8
EN
Q2
V
REF_AC
EN
D
Q
nQ2
ICS889833
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
Q3
nQ3
IDT
™
/ ICS
™
LVDS FANOUT BUFFER W/INTERNAL TERMINATION
1
ICS889833AK REV. B SEPTEMBER 9, 2008
ICS889833
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Type
Output
Description
Differential output pair. Normally terminated with 100
Ω
across the pair.
Unused outputs must be terminated with 100
Ω
across the pin (Q0/nQ0).
LVDS interface levels.
Differential output pair. Normally terminated with 100
Ω
across the pair.
Unused outputs must be terminated with 100
Ω
across the pin (Q1/nQ1).
LVDS interface levels.
Differential output pair. Normally terminated with 100
Ω
across the pair.
Unused outputs must be terminated with 100
Ω
across the pin (Q2/nQ2).
LVDS interface levels.
Positive supply pins.
Synchronizing output enable pin. When LOW, enables/disables outputs.
When HIGH, enables outputs when left open. Internally connected to a
37k
Ω
pull-up resistor. LVTTL / LVCMOS interface levels.
Inver ting differential clock input. R
T
= 50
Ω
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
- 1.4V
(approx.). Maximum sink/source current is 0.5mA.
Input termination center-tap. Each side of the differential input pair
terminates to a V
T
pin. The V
T
pins provide a center-tap to a termination
network for maximum interface flexibility.
Non-inver ting differential clock input. R
T
= 50
Ω
termination to V
T
.
3, 4
Q1, nQ1
Output
5, 6
7, 14
8
9
10
11
12
13
Q2, nQ2
V
DD
EN
nIN
V
REF_AC
V
T
IN
GND
Output
Power
Input
Input
Output
Input
Input
Power
Pullup
Power supply ground.
Differential output pair. Normally terminated with 100
Ω
across the pair.
15, 16
Q3, nQ3
Output
Unused outputs must be terminated with 100
Ω
across the pin (Q3nQ3).
LVDS interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
IDT
™
/ ICS
™
LVDS FANOUT BUFFER W/INTERNAL TERMINATION
2
ICS889833AK REV. B SEPTEMBER 9, 2008
ICS889833
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
IN
0
1
X
nIN
1
0
X
EN
1
1
0
0
1
0 (NOTE 1)
Outputs
Q0:Q3
nQ0:nQ3
1
0
1 (NOTE 1)
NOTE 1: On the next negative transition of the input signal (IN).
EN
V
DD
/2
t
S
t
H
V
DD
/2
nIN
IN
nQx
Qx
V
IN
→
t
PD
←
V
OUT
Swing
F
IGURE
1. EN T
IMING
D
IAGRAM
IDT
™
/ ICS
™
LVDS FANOUT BUFFER W/INTERNAL TERMINATION
3
ICS889833AK REV. B SEPTEMBER 9, 2008
ICS889833
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
±50mA
±100mA
±0.5mA
-40°C to +85°C
-65°C to 150°C
90.2°C/W (0 lfpm)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V; T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
100
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V; T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
Test Conditions
Minimum
2
-0.3
-125
Typical
Maximum
V
DD
+ 0.3
0.8
30
-300
Units
V
V
µA
µA
NOTE: Specs are design targets unless otherwise noted.
T
ABLE
4C. DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V; T
A
= -40°C
TO
85°C
Symbol
R
DIFF_IN
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF_AC
Parameter
Differential Input Resistance
Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Bias Voltage
(IN, nIN)
(IN, nIN)
(IN, nIN)
IN-to-VT
Test Conditions
Minimum
80
40
1.2
0
0.15
0. 3
V
DD
- 1.45
V
DD
- 1.35
V
DD
- 1.25
Typical
10 0
50
Maximum
120
60
V
DD
V
DD
- 0.15
1.7
Units
Ω
Ω
V
V
V
V
V
IDT
™
/ ICS
™
LVDS FANOUT BUFFER W/INTERNAL TERMINATION
4
ICS889833AK REV. B SEPTEMBER 9, 2008
ICS889833
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V; T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
250
500
1.15
Typical
325
650
1.35
1.55
50
Maximum
Units
mV
V
V
mV
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V; T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Maximum Output Frequency
Propagation Delay,
IN to Qx
(Differential); NOTE 1
Output Skew; NOTE 2, 3
Par t-to-Par t Skew; NOTE 3, 4
Cycle-to-Cycle Jitter, RMS; NOTE 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Total Jitter; NOTE 5
Random Jitter; NOTE 5
Deterministic Jitter; NOTE 5
Setup Time
Hold Time
EN to IN/nIN
EN to IN/nIN
20% - 80%
30 0
500
100
220
ƒ = 622.08MHz,
Integration Range: 12kHz - 20MHz
ƒ
≥
156.25MHz,
Integration Range: 12kHz - 20MHz
0.04
0.225
10
1
2
Condition
Minimum
2.0
300
520
40
200
0.2
Typical
Maximum
Units
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
jit
(cc)
t
jit
t
jit
(j)
t
jit
(rj)
t
jit
(tj)
t
S
t
H
t
R
/ t
F
Output Rise/Fall Time; NOTE 5
All parameters characterized at
≤
1.4GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Tested at ƒ
≤
750MHz.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER W/INTERNAL TERMINATION
5
ICS889833AK REV. B SEPTEMBER 9, 2008
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
