2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ICS85401
Features
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2:1 LVDS MUX
One LVDS output pair
Two differential clock inputs can accept: LVPECL, LVDS, CML
Maximum input/output frequency: 2.5GHz
Translates LVCMOS/LVTTL input signals to LVDS levels by
using a resistor bias network on nCLK0, nCLK1
Propagation delay: 460ps (maximum)
Part-to-part skew: 100ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Description
The ICS85401 is a high performance 2:1
Differential-to-LVDS Multiplexer and a member of
HiPerClockS™
the HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS85401 can also perform
differential translation because the differ-ential
inputs accept LVPECL, CML as well as LVDS levels.
The ICS85401 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space constrained
boards.
ICS
Block Diagram
CLK0
Pulldown
CLK0
Pullup/Pulldown
CLK1
Pulldown
CLK1
Pullup/Pulldown
0
Q
Q
1
Pin Assignment
GND
GND
CLK0 1
CLK0
2
16 15 14 13
12 GND
11 Q
10 Q
9 GND
5
nc
CLK1 3
CLK1 4
CLK_SEL
Pulldown
6
CLK_SEL
7
nc
ICS85401
16-Lead VFQFN
3mm x 3mm x 0.95mm
package body
K Package
Top View
IDT™ / ICS™
LVDS MULTIPLEXER
1
ICS85401AK REV. A MARCH 6, 2007
V
DD
V
DD
nc
8
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 7, 16
6
8, 13
9, 12, 14, 15
10, 11
Name
CLK0
CLK0
CLK1
CLK1
nc
CLK_SEL
V
DD
GND
Q, Q
Input
Input
Input
Input
Unused
Input
Power
Power
Output
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
No connect.
Clock select input. When HIGH, selects CLK1, CLK1 inputs.
When LOW, selects CLK0, CLK0 inputs.
LVCMOS / LVTTL interface levels.
Power supply pins.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to intenal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
37
37
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3. Control Input Function Table
Input
CLK_SEL
0
1
CLK_OUT
CLK
CLK0, CLK0
CLK1, CLK1
IDT™ / ICS™
LVDS MULTIPLEXER
2
ICS85401AK REV. A MARCH 6, 2007
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characterisitcs
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
51.5°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
40
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK0, CLK1
Input High Current
CLK0, CLK
CLK0, CLK1
I
IL
Input Low Current
CLK0, CLK
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
-150
-150
0.15
1.2
0.8
1.2
V
DD
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single-ended applications, the maximum input voltage for CLKx, CLKx is V
DD
+ 0.3V.
IDT™ / ICS™
LVDS MULTIPLEXER
3
ICS85401AK REV. A MARCH 6, 2007
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.05
1.15
Test Conditions
Minimum
200
Typical
350
Maximum
500
50
1.25
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(pp)
t
R
/ t
F
odc
MUX_
ISOLATION
Symbol
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
20% to 80%
125
49
-55
160
260
360
Test Conditions
Minimum
Typical
Maximum
>2.5
460
100
200
51
Units
GHz
ps
ps
ps
%
All parameters measured at £ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.Typical Phase Noise at 156.25MHz
IDT™ / ICS™
LVDS MULTIPLEXER
4
ICS85401AK REV. A MARCH 6, 2007
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information
VDD
,
,
SCOPE
VDD
,
Qx
CLK0,
CLK1
V
PP
3.3V±5%
POWER SUPPLY
+ Float GND –
Cross Points
V
LVDS
nQx
CMR
CLK0,
CLK1
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
Qx
Qx
Par t 1
CLK0,
CLK1
CLK0,
CLK1
Q
Qy
Par t 1
Qy
Q
t
PD
tsk(pp)
Part-to-Part Skew
Propagation Delay
Q
Q
t
PW
t
PERIOD
80%
Clock
Outputs
80%
V
OD
odc =
t
PW
t
PERIOD
20%
t
R
t
F
20%
x 100%
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT™ / ICS™
LVDS MULTIPLEXER
5
ICS85401AK REV. A MARCH 6, 2007
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