LVCMOS/LVTTL Clock Divider
ICS87001-01
DATASHEET
General Description
The ICS87001-01 is a low skew, ÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷8, ÷16
LVCMOS/LVTTL Fanout Buffer/Divider. The ICS87001-01 has
selectable clock inputs that accept single ended input levels. Output
enable pin controls whether the output is in the active or high
impedance state.
The ICS87001-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001-01 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
One LVCMOS / LVTTL output
Selectable LVCMOS / LVTTL clock inputs
Maximum output frequency: 250MHz
Part-to-part skew: 135ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
Block Diagram
CLK_SEL
Pulldown
N Output Divider
N2:N0
Pin Assignment
OE
V
DD
CLK0
CLK_SEL
CLK1
N2
N1
N0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DDO
nc
Q
nc
GND
nc
nc
GND
CLK0
Pulldown
0
CLK1
Pulldown
1
000
001
010
011
100
101
110
111
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
Q
ICS87001-01
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
Top View
N2:N0
Pulldown
OE
Pullup
3
ICS87001BG-01 REVISION A JULY 2, 2013
1
©2013 Integrated Device Technology, Inc.
ICS87001-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3, 5
4
6, 7, 8
9, 12
10, 11, 13, 15
14
16
Name
OE
V
DD
CLK0, CLK1
CLK_SEL
N2, N1, N0
GND
nc
Q
V
DDO
Input
Power
Input
Input
Input
Power
Unused
Output
Power
Pulldown
Pulldown
Pulldown
Type
Pullup
Description
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Power supply pin.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Input clock selection. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3.
Power supply ground.
No connect.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.465V
C
PD
Power Dissipation
Capacitance
V
DDO
= 2.625V
V
DDO
= 1.95V
V
DDO
= 3.3V±5%
R
OUT
Output Impedance
V
DDO
= 2.5V±5%
V
DDO
= 1.8V±0.15V
Test Conditions
Minimum
Typical
4
51
51
6
5
5
17
20
28
Maximum
Units
pF
k
k
pF
pF
pF
Function Tables
Table 3. Programmable Output Divider Function Table
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
2
Output Frequency (MHz)
250
125
83.333
62.5
50
41.667
31.25
15.625
©2013 Integrated Device Technology, Inc.
ICS87001BG-01 REVISION A JULY 2, 2013
ICS87001-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
100.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
55
5
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
55
5
Units
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
=1.8V ± 0.15V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
1.65
Typical
3.3
1.8
Maximum
3.465
1.95
55
5
Units
V
V
mA
mA
Table 4D. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
55
5
Units
V
V
mA
mA
ICS87001BG-01 REVISION A JULY 2, 2013
3
©2013 Integrated Device Technology, Inc.
ICS87001-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
Table 4E. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
=1.8V ± 0.15V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
1.65
Typical
2.5
1.8
Maximum
2.625
1.95
55
5
Units
V
V
mA
mA
Table 4F. LVCMOS/LVTTL DC Characteristics,
T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input
High Voltage
CLK_SEL,
CLK[0:1],
N[2:0]
V
IL
Input Low
Voltage
OE
CLK_SEL,
CLK[0:1],
N[2:0]
OE
Input
High
Current
CLK_SEL,
CLK[0:1],
N[2:0]
OE
Input
Low
Current
CLK_SEL,
CLK[0:1],
N[2:0]
OE
Output High Voltage;
NOTE 1
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.3V
V
OH
V
DDO
= 2.5V
V
DDO
= 1.8V
V
DDO
= 3.3V
V
OL
Output Low Voltage;
NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
V
DDO
= 2.5V
V
DDO
= 1.8V
I
OZL
I
OZH
-5
5
-5
-150
2.6
1.8
1.25
0.5
0.5
0.4
Minimum
2
1.7
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.6
0.7
0.5
150
5
Units
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
µA
µA
I
IH
I
IL
NOTE 1: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
ICS87001BG-01 REVISION A JULY 2, 2013
4
©2013 Integrated Device Technology, Inc.
ICS87001-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
t
PD
tsk(pp)
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay,
Low to High; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time
Output Disable Time
20% to 80%
0.4
40
0.6
N
2
N>2
3.6
4.3
4.6
5.5
Test Conditions
Minimum
Typical
Maximum
250
5.7
6.7
750
1.0
60
10
10
Units
MHz
ns
ns
ps
ns
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
IN
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
t
PD
tsk(pp)
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay,
Low to High; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time
Output Disable Time
20% to 80%
0.4
40
0.7
N
2
N>2
3.5
4.5
4.8
5.7
Test Conditions
Minimum
Typical
Maximum
250
6.2
6.9
590
1.1
60
10
10
Units
MHz
ns
ns
ps
ns
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
IN
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ICS87001BG-01 REVISION A JULY 2, 2013
5
©2013 Integrated Device Technology, Inc.
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