82C82
March 1997
CMOS Octal Latching Bus Driver
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Features
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NUMBER
CP82C82
IP82C82
CS82C82
IS82C82
CD82C82
ID82C82
MD82C82/B
8406701RA
MR82C82/B
84067012A
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD #
-55
o
C to +125
o
C 20 Pad CLCC
SMD #
J20.A
20 Ld CERDIP F20.3
20 Ld PLCC
N20.35
PACKAGE
20 Ld PDIP
PKG. NO.
E20.3
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
DI
2
DI
1
DI
0
DO
0
V
CC
STB
X
H
H
DI
3
4
DI
4
5
DI
5
6
DI
6
7
DI
7
8
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
H
L
X
†
↓
TRUTH TABLE
OE
H
L
L
L
DI
X
L
H
X
DO
Hi-Z
L
H
†
3
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
1
2
3
4
5
6
7
8
9
20 V
CC
19 DO
0
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
13 DO
6
12 DO
7
11 STB
2
1
20
19
= Logic One
= Logic Zero
= Don’t Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
↓
= Neg. Transition
PIN NAMES
9
OE
10
GND
11
STB
12
DO
7
13
DO
6
GND 10
PIN
DI
0
-DI
7
DO
0
-DO
7
STB
OE
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2975.1
4-274
82C82
Functional Diagram
DI
O
D Q
CLK
DO
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
STB
OE
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unre-
lated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between V
CC
and GND when
the signal is at or near the input switching threshold. Addition-
ally, if the driving signal becomes high impedance (“float” con-
dition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE =
logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the V
CC
and ground power
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from V
CC
to
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the max-
imum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
V
CC
V
CC
P
P
OE
STB
DATA IN
N
N
N
N
N
P
INTERNAL
DATA
DATA IN
V
CC
N
P
P
INTERNAL
DATA
V
CC
P
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
4-275
82C82
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C82 data sheet is
determined by:
I
=
C
L
(dv/dt)
(EQ. 1)
where tR = 20ns, V
CC
= 5.0V, C
L
= 300pF on each of eight
outputs.
I =
(
8 x 300 x 10
-12
)x
(5.0V x 0.8)/
(
20 x 10
–
9
)
= 480mA
(EQ. 4)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
I
=
C
L
(
V
CC
x 80%
)
-----------------------------------
tR/tF
(EQ. 2)
(EQ. 3)
This current spike may cause a large negative voltage spike
on V
CC
, which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1µF
ceramic disc decoupling capacitor be placed between V
CC
and GND at each device, with placement being as near to
the device as possible.
V
CC
P
V
CC
P
ALE
MULTIPLEXED
BUS
ICC
STB
ADDRESS
ADDRESS
DATA IN
N
N
P
INTERNAL
DATA
N
FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS
4-276
82C82
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θ
JA
θ
JC
o
C/W
CERDIP . . . . . . . . . . . . . . . . . . . . . . . . 75
18
o
C/W
CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85
o
C/W
22
o
C/W
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
(PLCC Lead Tips Only)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5.0V
±10%;
T
A
= 0
o
C to +70
o
C (C82C82);
T
A
= -40
o
C to +85
o
C (I82C82);
T
A
= -55
o
C to +125
o
C (M82C82)
MAX
-
-
0.8
-
-
0.4
1.0
10.0
UNITS
V
V
V
V
V
V
µA
µA
µA
I
OH
= -8mA, OE = GND
I
OH
= -100µA, OE = GND
I
OL
= 8mA, OE = GND
V
IN
= GND or V
CC
, DIP Pins 1-9, 11
V
O
= GND or V
CC
, OE
≥
V
CC
-0.5V
DIP Pins 12-19
V
IN
= V
CC
or GND, V
CC
= 5.5V, Outputs Open
T
A
= +25
o
C, V
CC
= 5V, Typical (See Note 2)
TEST CONDITIONS
C82C82, I82C82 (Note 1)
M82C82 (Note 1)
SYMBOL
V
IH
PARAMETER
Logical One Input Voltage
MIN
2.0
2.2
V
IL
V
OH
Logical Zero Input Voltage
Logical One Output Voltage
-
2.9
V
CC
-0.4V
V
OL
II
IO
Logical Zero Output Voltage
Input Leakage Current
Output Leakage Current
-
-1.0
-10.0
ICCSB
Standby Power Supply Cur-
rent
Operating Power Supply
Current
-
10
ICCOP
-
1
mA/MHz
NOTES:
1. V
IH
is measured by applying a pulse of magnitude = V
IH
min to one data input at a time and checking the corresponding device output
for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at V
CC
-0.4.
2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz
µP,
ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
SYMBOL
C
IN
C
OUT
T
A
= +25
o
C
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
13
20
UNITS
pF
pF
TEST CONDITIONS
Freq = 1MHz, all measurements are
referenced to device GND
4-277
82C82
AC Electrical Specifications
V
CC
= 5.0V
±10%;
T
A
= 0
o
C to +70
o
C (C82C82);
C
L
= 300pF (Note 1), Freq = 1MHz T
A
= -40
o
C to +85
o
C (I82C82);
T
A
= -55
o
C to +125
o
C (M82C82)
MIN
-
-
-
-
0
25
25
-
MAX
35
55
35
50
-
-
-
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
SYMBOL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TIVOV
TSHOV
TEHOZ
TELOV
TIVSL
TSLIX
TSHSL
TR, TF
PARAMETER
Propagation Delay Input to Output
Propagation Delay STB to Output
Output Disable Time
Output Enable Time
Input to STB Setup Time
Input to STB Hold Time
STB High Time
Input Rise/Fall Times
NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between V
IL
- 0.4V and V
IH
+0.4V.
Timing Waveforms
TR, TF (8)
INPUTS
2.0V
0.8V
TIVSL (5)
STB
TSHSL (7)
OE
TIVOV
(1)
OUTPUTS
TSHOV (2)
TSLIX
(6)
TEHOZ (3)
VOH -0.1V
VOL +0.1V
TELOV (4)
2.4V
0.8V
Test Load Circuits
1.7V
0.6V
3.3V
150Ω
OUTPUT
TEST
POINT
300Ω
OUTPUT
TEST
POINT
300Ω
OUTPUT
TEST
POINT
300pF
(NOTE)
50pF
(NOTE)
50pF
(NOTE)
TIVOV, TSHOV, TELOV
TEHOZ OUTPUT HIGH DISABLE
TEHOZ OUTPUT LOW DISABLE
NOTE: Includes stray and jig capacitance.
4-278
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