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IDT7026S15J8

产品描述Dual-Port SRAM, 16KX16, 15ns, CMOS, PQCC84, PLASTIC, LCC-84
产品类别存储    存储   
文件大小179KB,共18页
制造商IDT (Integrated Device Technology)
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IDT7026S15J8概述

Dual-Port SRAM, 16KX16, 15ns, CMOS, PQCC84, PLASTIC, LCC-84

IDT7026S15J8规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码LCC
包装说明QCCJ, LDCC84,1.2SQ
针数84
Reach Compliance Codenot_compliant
ECCN代码EAR99
Base Number Matches1

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HIGH-SPEED
16K X 16 DUAL-PORT
STATIC RAM
Features
x
x
IDT7026S/L
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Military: 20/25/35/55ns (max.)
Low-power operation
– IDT7026S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multi-
plexed bus compatibility
x
x
x
x
x
x
x
x
IDT7026 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA and 84-pin PLCC
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
I/O
Control
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
A
13L
A
0L
(1,2)
BUSY
R
Address
Decoder
14
(1,2)
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
ARBITRATION
SEMAPHORE
LOGIC
CE
R
SEM
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs are non-tri-stated push-pull.
M/
S
SEM
R
2939 drw 01
MARCH 2000
1
©2000 Integrated Device Technology, Inc.
DSC 2939/11

 
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