HIGH-SPEED 32/16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
IDT709379/69L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
– Insustrial: 9ns (max.)
Low-power operation
– IDT709379/69L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b a
1a 0a
0a 1a
a
0b 1b
b
0/1
FT
/PIPE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
A
14L
(1)
A
0L
CLK
L
Counter/
Address
Reg.
I/O
Control
I/O
9R
-I/O
17R
I/O
Control
I/O
0R
-I/O
8R
A
14R
(1)
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
4845 drw 01
NOTE:
1. A
14X
is a NC for IDT709369.
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-4845/8
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709379/69 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by
CE
0
and CE
1,
permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devices typically operate on only 1.2W of power.
Pin Configurations
(1,2,3)
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
GND
GND
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
(1)
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
V
CC
FT/PIPE
L
I/O
17L
I/O
16L
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
709379/69PF
PN100
(5)
100-Pin TQFP
Top View
(6)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
(1)
NC
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
R/W
R
GND
OE
R
.
FT/PIPE
R
I/O
17R
GND
I/O
16R
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
4845 drw 02
NOTES:
1. A14x is a NC for IDT709369.
2. All V
CC
pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
CC
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O1
L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
CC
I/O
7R
I/O
8R
I/O
9R
I/O
10R
2
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
(1)
I/O
0L
- I/O
17L
CLK
L
UB
L
LB
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
(1)
I/O
0R
- I/O
17R
CLK
R
UB
R
LB
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
CC
GND
Names
Chip Enables
(3)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Upper Byte Select
(2)
Lower Byte Selectt
(2)
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
4845 tbl 01
NOTES:
1. A14x is a NC for IDT709369.
2.
LB
and
UB
are single buffered regardless of state of
FT/PIPE.
3.
CEo
and CE
1
are single buffered when
FT/PIPE
= V
IL
,
CEo
and CE
1
are double buffered when
FT/PIPE
= V
IH
,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
L
L
L
L
L
CE
1
X
L
H
H
H
H
H
H
H
H
UB
X
X
H
L
H
L
L
H
L
L
LB
X
X
H
H
L
L
H
L
L
L
R/W
X
X
X
L
L
L
H
H
H
X
Upper Byte
I/O
9-17
High-Z
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Lower B
yte
I/O
0-8
High-Z
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected—Power Down
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
4845 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
3
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control
(1,2,6)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Reset to Address 0
4845 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB,
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
is independent of all other signals including
CE
0
, CE
1
,
UB
and
LB.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB
and
LB.
6. While an external address is being loaded (ADS = V
IL
), R/W = V
IH
is recommended to ensure data is not written arbitrarily.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
(2)
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
CC
5.0V
+
10%
5.0V
+
10%
4845 tbl 04
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(2)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(1)
0.8
Unit
V
V
V
V
4845 tbl 05
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
TERM
must not exceed V
CC
+ 10%.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Capacitance
(1)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4845 tbl 07
Output Capacitance
T
BIAS
T
STG
T
JN
I
OUT
-55 to +125
-65 to +150
+150
50
o
o
o
C
C
C
mA
4845 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
4
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(V
CC
= 5.0V ± 10%)
709379/69L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4845 tbl 08
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(3)
(V
CC
= 5V ± 10%)
709379/69L7
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
Outputs Disabled
f = f
MAX
(1)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs
Disabled, f=f
MAX
(1)
Both Ports CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Disabled, f = f
MAX
(1)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
L
L
L
L
L
L
L
L
L
L
Typ.
(4)
250
____
709379/69L9
Com'l
& Ind
Typ.
(4)
250
300
80
95
175
175
Max.
400
430
135
160
275
295
709379/69L12
Com'l Only
Typ.
(4)
230
____
Max.
440
____
Max.
355
____
Unit
mA
I
SB1
65
____
145
____
70
____
110
____
mA
I
SB2
160
____
295
____
150
____
240
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
0.2
____
5.0
____
0.5
0.5
3.0
6.0
0.5
____
3.0
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
150
____
290
____
170
190
270
290
140
____
225
____
mA
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
CC
= 5V, TA = 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 150mA (Typ).
5. CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means
CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
4845 tbl 09
5
6.42
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
