74F544 Octal Registered Transceiver
April 1988
Revised October 2000
74F544
Octal Registered Transceiver
General Description
The 74F544 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA. The 74F544 inverts data in
both directions.
Features
s
8-bit octal transceiver
s
Back-to-back registers for storage
s
Separate controls for data flow in each direction
s
A outputs sink 24 mA, B outputs sink 64 mA
Ordering Code:
Order Number
74F544SC
74F544MSA
74F544SPC
Package Number
M24B
MSA24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009555
www.fairchildsemi.com
74F544
Unit Loading/Fan Out
U.L.
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
Description
HIGH/LOW
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40(33.3)
3.5/1.083
600/106.6(80)
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
70
µ
A/
−
650
µ
A
−
3 mA/24 mA (20 mA)
70
µ
A/
−
650
µ
A
−
12 mA/64 mA (48 mA)
Functional Description
The 74F544 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A
0
–A
7
or
take data from B
0
–B
7
, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Data I/O Control Table
Inputs
CEAB
H
X
L
X
L
LEAB
X
H
L
X
X
OEAB
X
X
X
H
L
Latch
Status
Latched
Latched
Transparent
—
—
Output
Buffers
High Z
—
—
High Z
Driving
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note:
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F544
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Min
2.0
0.8
−1.2
10% V
CC
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
Output LOW
Voltage
I
IH
Input HIGH
Current
I
BVI
Input HIGH Current
Breakdown Test
I
BVIT
Input HIGH Current
Breakdown (I/O)
I
CEX
V
ID
I
OD
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
Input LOW Current
4.75
3.75
−0.6
−1.2
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
−60
−100
I
ZZ
I
CCH
I
CCL
I
CCZ
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
70
85
83
70
−650
−150
−225
500
105
130
125
10% V
CC
10% V
CC
2.5
2.4
2.0
2.7
2.7
0.5
0.55
20.0
5.0
7.0
V
µA
µA
Min
V
Min
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA,
(except A
n
, B
n
)
I
OH
= −1
mA (A
n
)
I
OH
= −3
mA (A
n
, B
n
)
I
OH
= −15
mA (B
n
)
I
OH
= −1
mA (A
n
)
I
OH
= −3
mA (A
n
, B
n
)
I
OL
=
24 mA (A
n
)
I
OL
=
64 mA (B
n
)
V
IN
=
2.7V (except A
n
, B
n
)
V
IN
=
7.0V (except A
n
, B
n
)
V
IN
=
5.5V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (OEAB, OEBA)
V
IN
=
0.5V (CEAB, CEBA)
V
OUT
=
2.7V (A
n
, B
n
)
V
OUT
=
0.5V (A
n
, B
n
)
V
OUT
=
0V (A
n
)
V
OUT
=
0V (B
n
)
V
OUT
=
5.25V (A
n
, B
n
)
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
V
OH
Output HIGH
Voltage
Max
Max
0.5
mA
µA
V
µA
Max
250
Max
0.0
0.0
mA
µA
µA
mA
µA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
Max
Max
3
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74F544
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA to A
n
Propagation Delay
LEAB to B
n
Output Enable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
Output Disable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
1.0
2.5
6.0
5.5
8.0
10.5
2.0
2.0
10.0
9.5
1.0
2.5
9.0
11.5
6.0
4.0
6.0
4.0
3.0
4.0
10.0
7.0
10.0
7.0
7.0
7.5
13.0
9.5
13.0
9.5
9.0
10.5
6.0
4.0
6.0
4.0
3.0
4.0
18.0
11.5
18.0
11.5
11.0
13.0
6.0
4.0
6.0
4.0
3.0
4.0
14.5
10.5
14.5
10.5
10.0
12.0
ns
ns
ns
3.0
3.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
7.0
5.0
Max
9.5
6.5
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
3.0
2.5
Max
12.0
8.5
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
3.0
3.0
Max
10.5
7.5
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(L)
Setup Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Hold Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Latch Enable, B to A
Pulse Width, LOW
3.0
3.0
3.0
3.0
6.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
3.0
3.0
3.0
3.0
9.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.0
3.0
3.0
7.5
ns
ns
Max
Units
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4
74F544
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
5
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