Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Rev. 8 — 26 June 2013
Product data sheet
1. General description
The 74LVC244A; 74LVCH244A is an octal non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.
A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVCH244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
CC
= 0 V
Bus hold on all data inputs (74LVCH244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC244AD
74LVCH244AD
74LVC244ADB
74LVCH244ADB
74LVC244APW
74LVCH244APW
74LVC244ABQ
74LVCH244ABQ
74LVC244ABX
74LVCH244ABX
40 C
to +125
C
DHXQFN20
40 C
to +125
C
DHVQFN20
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
40 C
to +125
C
Name
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; body 4.5
2.5
0.5 mm
SOT1045-2
4. Functional diagram
2
18
17
3
1A0
1Y0
2A0
2Y0
1A1
4
16
1Y1
2A1
15
5
2Y1
1A2
6
14
1Y2
2A2
13
7
2Y2
1A3
1OE
8
1
12
1Y3
2A3
2OE
11
19
9
2Y3
mna874
Fig 1.
Logic symbol
74LVC_LVCH244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 26 June 2013
2 of 19
NXP Semiconductors
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
1
EN
18
16
14
12
8
1
1A3
1OE
1Y3
12
2
4
6
8
17
2A0
2Y0
3
15
19
EN
13
11
13
15
17
mna873
2A1
2Y1
5
2A2
2Y2
7
9
7
5
3
19
11
2A3
2OE
2Y3
9
mna875
Fig 2.
IEC logic diagram
Fig 3.
Functional diagram
74LVC_LVCH244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 26 June 2013
3 of 19
NXP Semiconductors
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74LVC244A
74LVCH244A
1OE
2
3
4
5
6
7
8
9
GND 10
2A3 11
GND
(1)
1
1A0
2Y0
terminal 1
index area
74LVC244A
74LVCH244A
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
001aad113
20 V
CC
19
2OE
18
1Y0
17
2A0
16
1Y1
15
2A1
14
1Y2
13
2A2
12
1Y3
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND 10
001aad114
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO20 and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20 and
DHXQFN20
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2A0, 2A1, 2A2, 2A3
1Y0, 1Y1, 1Y2, 1Y3,
V
CC
Pin description
Pin
1, 19
2, 4, 6, 8
3, 5, 7, 9
10
Description
output enable input (active low)
data input
data output
ground (0 V)
17, 15, 13, 11 data input
18, 16, 14, 12 data output
20
supply voltage
74LVC_LVCH244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 26 June 2013
4 of 19
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
