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74LVCH162374A
16-bit edge-triggered D-type flip-flop with 30
series
termination resistors; 5 V input/output tolerant; 3-state
Rev. 4 — 22 January 2013
Product data sheet
1. General description
The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of
two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE)
are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When
disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these
devices in mixed 3.3 V and 5 V applications. The flip-flops store the state of their
individual D-inputs that meet the set-up and hold time requirements on the LOW to HIGH
CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
To reduce line noise, 30
series termination resistors are included in both high and low
output stages.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30
resistors; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVCH162374ADGG
74LVCH162374ADL
40 C
to +125
C
40 C
to +125
C
Name
TSSOP48
SSOP48
Description
Version
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
Type number
4. Functional diagram
1
1OE
48
1CP
24
2OE
25
2CP
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1CP
48
2CP
25
001aaa253
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
001aaa254
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
24
2OE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVCH162374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 22 January 2013
2 of 17
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30
resistors; 3-state
1D0
D
CP
FF1
Q
1Q0
2D0
D
CP
FF2
Q
2Q0
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
001aaa255
Fig 3.
Logic diagram
V
CC
data input
to internal circuit
mgu771
Fig 4.
Bus hold circuit
74LVCH162374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 22 January 2013
3 of 17
NXP Semiconductors
74LVCH162374A
16-bit edge-triggered D-type flip-flop; 30
resistors; 3-state
5. Pinning information
5.1 Pinning
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48
1CP
47
1D0
46
1D1
45
GND
44
1D2
43
1D3
42
V
CC
41
1D4
40
1D5
39
GND
38
1D6
37
1D7
36
2D0
35
2D1
34
GND
33
2D2
32
2D3
31
V
CC
30
2D4
29
2D5
28
GND
27
2D6
26
2D7
25
2CP
001aab023
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
2Q2
16
2Q3
17
V
CC
18
2Q4
19
2Q5
20
GND
21
2Q6
22
2Q7
23
2OE
24
162374A
Fig 5.
Pin configuration SSOP48 and TSSOP48
5.2 Pin description
Table 2.
Symbol
1OE
2OE
1CP
2CP
GND
V
CC
1Q[0:7]
2Q[0:7]
1D[0:7]
2D[0:7]
Pin description
Pin
1
24
48
25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
Description
output enable input (active LOW)
output enable input (active LOW)
clock input
clock input
ground (0 V)
supply voltage
data output
data output
data input
data input
74LVCH162374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 22 January 2013
4 of 17
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