74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs
November 1988
Revised March 2005
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to 74AC373 and 74ACT373
s
3-STATE outputs for bus interfacing
s
Outputs source/sink 24 mA
s
74ACT573 has TTL-compatible inputs
Ordering Code:
Order Number
74AC573SC
74AC573SJ
74AC573MTC
74AC573PC
74ACT573SC
74ACT573SCX_NL
(Note 1)
74ACT573SJ
74ACT573MTC
74ACT573PC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009973
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74AC573 • 74ACT573
Logic Symbols
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
IEEE/IEC
O
0
–O
7
Truth Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
n
H
L
O
0
Z
Connection Diagram
H
L
Z
X
O
0
HIGH Voltage
LOW Voltage
High Impedance
Immaterial
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Functional Description
The 74AC573 and 74ACT573 contain eight D-type latches
with 3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D-type input changes.
When LE is LOW the latches store the information that was
present on the D-type inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the buff-
ers are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74AC573 • 74ACT573
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
(PDIP)
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
CC
(Note 4)
I
OZ
Maximum Input Leakage Current
Minimum Dynamic
Output Current (Note 5)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5:
Maximum test duration 2.0 ms, one output loaded at a time.
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
25
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
Units
V
OUT
V
Conditions
0.1V
Guaranteed Limits
or V
CC
0.1V
V
OUT
V
0.1V
or V
CC
0.1V
I
OUT
50
P
A
V
V
IN
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
I
OH
I
OH
I
OH
12 mA
24 mA
24 mA (Note 3)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 3)
V
CC
, GND
1.65V Max
3.85V Min
V
CC
or GND
V
IL
, V
IH
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
V
I
OUT
V
IN
0.44
0.44
0.44
V
I
OL
I
OL
I
OL
V
I
5.5
5.5
5.5
5.5
5.5
r
0.1
r
1.0
75
P
A
mA
mA
V
OLD
V
OHD
V
IN
75
4.0
40.0
P
A
P
A
r
0.25
r
2.5
V
I
(OE)
V
I
V
O
V
CC
, GND
V
CC
, GND
3
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74AC573 • 74ACT573
AC Electrical Characteristics for AC
V
CC
Symbol
t
PHL
t
PLH
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
Note 6:
Voltage Range 5.0 is 5.0V
r
0.5V
Voltage Range 3.3 is 3.3V
r
0.3V
T
A
C
L
Min
0.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
25
q
C
50 pF
Typ
8.5
5.5
8.5
6.0
8.5
6.0
9.0
6.0
Max
10.5
7.0
12.0
8.0
13.0
8.5
14.5
9.5
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
11.0
7.5
12.5
8.5
13.5
9.0
15.0
10.0
ns
ns
ns
ns
Units
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
AC Operating Requirements for AC
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
(V)
(Note 7)
3.3
5.0
3.3
5.0
3.3
5.0
Note 7:
Voltage Range 5.0 is 5.0V
r
0.5V
Voltage Range 3.3 is 3.3V
r
0.3V
T
A
C
L
Typ
0
0
0
0
2.0
2.0
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
Guaranteed Minimum
3.0
3.0
1.5
1.5
4.0
4.0
3.0
3.0
1.5
1.5
4.0
4.0
ns
ns
ns
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4
74AC573 • 74ACT573
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
I
CC
/Input
Minimum Dynamic
Output Current (Note 9)
Maximum Quiescent
Supply Current
Note 8:
All outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
V
CC
(V)
4.5
5.5
4.5
T
A
Typ
1.5
1.5
1.5
5.5
4.49
5.49
25
q
C
2.0
2.0
0.8
1.5
4.4
5.4
3.86
4.86
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
I
OH
24 mA
24 mA (Note 8)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 8)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
CC
2.1V
1.65V Max
3.85V Min
V
CC
or GND
0.001
0.001
0.1
0.1
0.36
0.36
V
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
I
V
O
V
I
5.5
5.5
5.5
5.5
5.5
5.5
0.6
r
0.1
r
0.25
r
1.0
r
2.5
1.5
75
P
A
P
A
mA
mA
mA
V
OLD
V
OHD
V
IN
75
4.0
40.0
P
A
AC Electrical Characteristics for ACT
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
2.5
1.5
5.5
5.5
6.5
5.0
10.0
9.5
11.0
8.5
1.5
1.5
1.5
1.0
11.0
10.5
12.5
9.5
ns
ns
ns
ns
5.0
2.5
5.5
9.5
2.0
10.5
ns
5.0
3.0
6.0
10.5
2.5
12.0
ns
(V)
(Note 10)
5.0
Min
2.5
T
A
C
L
25
q
C
50 pF
Typ
6.0
Max
10.5
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
12.0
ns
Units
Min
2.0
Note 10:
Voltage Range 5.0 is 5.0V
r
0.5V
5
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