Solid State Devices, Inc.
14830 Valley View Blvd * La Mirada, Ca 90638
Phone: (562) 404-7855 * Fax: (562) 404-1773
ssdi@ssdi-power.com * www.ssdi-power.com
SFF25P20S2I
series
25 AMP / 200 Volts
125 mΩ
P-Channel MOSFET
Features:
•
•
•
•
•
•
polySi gate cell structure
Low ON-resistance
UIS (unclamped inductive switching) rated
Hermetically Sealed, Isolated Package
Low package inductance
Stress relief provided by flexible leads –
several options available
Improved (R
DS(ON)
Q
G
) figure of merit
TX TXV S Level screening available
DESIGNER’S DATA SHEET
SMD 2 isolated
NOTE: SEE DASH# DEFINITION TABLE FOR AVAILABLE
LEAD FORMING CONFIGURATION
•
•
Maximum Ratings
Drain - Source Voltage
Gate – Source Voltage
Max. Continuous Drain Current
Max. Instantaneous Drain Current (Tj limited)
Max. Avalanche current
Repetitive Avalanche Energy
Total Power Dissipation
Operating & Storage Temperature
Maximum Thermal Resistance
Junction to Case
@ T
C
= 25ºC
@ T
C
= 25ºC
@ T
C
= 25ºC
Symbol
V
DSS
V
GS
I
D1
I
D3
I
AR
E
AR
P
D
T
OP
& T
STG
R
0JC
Symbol
BV
DSS
R
DS(on)
V
GS(th)
I
GSS
I
DSS
Value
-200
±20
25
95
25
30
250
-55 to +150
0.5
Units
V
V
A
A
A
mJ
W
ºC
ºC/W
Electrical Characteristics (
@25
o
C, unless otherwise specified)
Drain to Source Breakdown Voltage
Drain to Source On State Resistance
Gate Threshold Voltage
Gate to Source Leakage
Zero Gate Voltage Drain Current
V
GS
= 0V, I
D
= 250µA
V
GS
= 10V, I
D
= 12A, Tj= 25
o
C
V
GS
= 10V, I
D
= 25A, Tj= 25
o
C
V
DS
= V
GS
, I
D
= 250µA
V
GS
= ±20V
V
DS
= 160V, V
GS
= 0V, T
j
= 25
o
C
V
DS
= 160V, V
GS
= 0V, T
j
= 125
o
C
Min
200
––
––
3.0
––
––
––
Typ Max
––
110
125
––
––
––
––
––
120
––
5.0
±100
25
1
Units
V
mΩ
V
nA
µA
mA
NOTE:
All specifications are subject to change without notification.
SCD's for these devices should be reviewed by SSDI prior to release.
DATA SHEET #: FT0009A
DOC
Solid State Devices, Inc.
14830 Valley View Blvd * La Mirada, Ca 90638
Phone: (562) 404-7855 * Fax: (562) 404-1773
ssdi@ssdi-power.com * www.ssdi-power.com
SFF25P20S2I
series
Symbol
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
C
iss
C
oss
C
rss
Electrical Characteristics (
@25
o
C, unless otherwise specified)
Forward Transconductance
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Turn on Delay Time
Rise Time
Turn off Delay Time
Fall Time
Diode Forward Voltage
Diode Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
NOTES:
Pulse Test: Pulse Width = 300µsec, Duty Cycle = 2%.
.50 MIN
.920
Min
5
––
––
––
––
––
––
––
––
––
––
––
––
Typ Max
12
150
35
70
35
30
70
30
2.0
250
4200
1200
350
––
––
––
––
––
––
––
3.0
––
––
––
––
Units
Mho
nC
V
DS
= 10V, I
D
= 24A, T
j
= 25
o
C
V
GS
= 10V
V
DS
= 100V
I
D
= 12A
V
GS
= 10V
V
DS
= 100V
I
D
= 12A
R
G
= 4.7Ω
I
F
= 25A, V
GS
= 0V
I
F
= 24A, di/dt = 100A/usec
V
GS
= 0V
V
DS
= 25V
f = 1 MHz
nsec
V
nsec
pF
.50 MIN
1
.610
2
.290
3
.190
.160
.014
.006
A
.160
MAX
3x .11±.02
2x .050
.220
.570
.510
.610
TOLERANCES:
(UNLESS OTHERWISE SPECIFIED)
.XX ± .02
.XXX ± .010
880
LEAD FORMING CONFIGURATIONS
SMD2I dash#
-01
-02
-03
0.062”
0.000”
0.097”
A
Package
SMD2I
PIN ASSIGNMENT (Standard)
Drain
Source
Pin 1
Pin 2
Gate
Pin 3
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
