CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING AND
BYTE SWAPPING 64 x 36 x 2
FEATURES:
•
IDT723616
•
•
•
•
•
•
•
•
•
•
Two independent FIFOs (64 X 36 storage capacity each) buffer
data between bidirectional 36-bit port A and two unidirectional
18/9-bit ports (Port B transmits, Port C receives)
Clock frequencies up to 67 MHz (10 ns access time)
Free-running clock lines for each port: CLKA, CLKB and CLKC,
may be asynchronous or coincident (simultaneous reading and
writing of data is permitted)
IDT Standard timing
Empty flag functions:
EFA
(synchronized by CLKA) and
EFB
(synchronized by CLKB)
Full flag functions:
FFA
(synchronized by CLKA) and
FFC
(synchronized by CLKC)
Programmable Almost-Empty and Almost-Full flags; each has
four default offsets (4, 8, 12 and 16)
Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C
Byte order swapping on ports B and C
Passive parity checking on ports A and C
Parity generation can be selected for ports A and B
Master Reset clears data and configures FIFO
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Width can be easily expanded by adding FIFOs
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
High performance sub-micron CMOS technology
Industrial temperature range (–40
o
C to +85
o
C) is available
DESCRIPTION:
The IDT723616 is a monolithic, high-speed, low-power, CMOS Triple Bus
SyncFIFO™ (clocked) memory which supports clock frequencies up to 67
MHz and has read access times as fast as 10 ns. Two independent 64 x 36
dual-port SRAM FIFOs on board each chip buffer data between a bidirectional
36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data,
Port C receives data.) FIFO data can be read out of ports B and written into
port C using either 18-bit or 9-bit formats.
Reset (RST) initializes the read and write pointers to the first location of the
memory array and selects one of four possible default flag offset settings: 4, 8,
12 or 16.
Each FIFO has flags to indicate empty and full conditions and two program-
mable flags (Almost-Full and Almost-Empty) to indicate when a selected
number of words is stored in memory. Data on Port B can be accessed in 18-
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
PEFA
Bus Matching and
Byte Swapping
Parity
Generation
Input
Register
RAM
ARRAY
64 x 36
Output
Register
Port-A
Control
Logic
Parity
check
PGB
18
B
0
- B
17
CLKB
RENB
Port-B
Control
Logic
Write
Pointer
36
Read
Pointer
Status Flag
Logic
Common
Port
Control
Logic
(B and C)
EFB
AEB
SWB0
SWB1
SWC0
SWC1
SIZ0
SIZ1
FFC
AFC
FFA
AFA
FIFO 1
FS0
FS1
A
0
- A
35
EFA
AEA
FIFO 2
Programmable Flag
Offset Registers
Status Flag
Logic
Read
Pointer
Write
Pointer
Parity
Generation
ODD/EVEN
Output
Register
Input
Register
RAM
ARRAY
64 x 36
Bus Matching and
Byte Swapping
RST
FIFO2,
FIFO1
Reset/
Control
Logic
36
Parity
Check
PEFC
18
C
0
- C
17
CLKC
WENC
3520 drw01
Port-C
Control
Logic
PGA
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2002
DSC-3107/1
IDT723616 CMOS TRIPLE BUS SyncFIFO™ WITH
™
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
bit and 9-bit formats. FIFO Data on Port C can be input in 18-bit and 9-bit formats.
Byte-order swapping on ports B and C is possible with any bus size selection.
Parity is checked passively on ports A and C and may be ignored if not desired.
Parity generation can be selected for data read from ports A and B. Two or
more devices can be used in parallel to create wider or deeper FIFO
configurations.
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or
buses controlled by a synchronous interface.
PIN CONFIGURATION
GND
A27
A28
A29
GND
Vcc
A30
A31
A32
A33
A34
A35
GND
B17
B16
B15
B14
B13
B12
GND
Vcc
B11
B10
B9
Vcc
GND
INDEX
CLKA
W/RA
NC
Vcc
PGA
PEFA
NC
SWC1
FS1
FS0
ODD/EVEN
RST
GND
NC
SWC0
SWB1
SWB0
SIZ1
SIZ0
NC
PEFC
PGB
Vcc
NC
CLKC
CLKB
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Vcc
A26
A25
A24
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
Vcc
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
AFA
FFA
CSA
ENA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
B8
B7
B6
B5
B4
B3
GND
B2
B1
B0
C17
C16
C15
C14
C13
C12
C11
C10
GND
C9
C8
C7
Vcc
C6
C5
C4
C3
GND
C2
C1
C0
EFB
AEB
AFC
FFC
RENB
WENC
3520 drw02
NOTE:
1. NC - No internal connection.
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2
IDT723616 CMOS TRIPLE BUS SyncFIFO™ WITH
™
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
This FIFO employs IDT Standard Mode timing; that is to say, the first word
written to an empty FIFO is deposited into the memory array. A read operation
is required to access that word (along with all other words residing in memory).
Each FIFO has an Empty Flag (EFA and
EFB)
and a Full Flag (FFA and
FFC). EF
indicates whether or not the FIFO memory is empty.
FF
shows
whether the memory is full or not.
Each FIFO has a programmable Almost-Empty flag (AEA and
AEB)
and a
programmable Almost-Full flag (AFA and
AFC). AEA
and
AEB
indicate when
a selected number of words written to FIFO memory achieve a predetermined
"almost-empty state".
AFA
and
AFC
indicate when a selected number of words
written to the memory achieve a predetermined "almost-full state".
FFA, FFC, AFA
and
AFC
are two-stage synchronized to the port clock that
writes data into its array.
EFA, EFB, AEA,
and
AEB
are two-stage synchronized
to the port clock that reads data from its array. Four default offset settings are
also provided. The
AEA
and
AEB
threshold can be set at 4, 8, 12 or 16 locations
from the empty boundary and the
AFA
and
AFC
threshold can be set at 4, 8,
12 or 16 locations from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Reset.
Two or more FIFOs may be used in parallel to create wider data paths. Such
a width expansion requires no additional, external components.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating
control inputs) will immediately take the device out of the Power Down state.
The IDT723616 are characterized for operation from 0°C to 70°C. They
are fabricated using IDT’s high speed, submicron CMOS technology.
3
IDT723616 CMOS TRIPLE BUS SyncFIFO™ WITH
™
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
A0-A35
AEA
AEB
AFA
AFC
B0-B17
C0-C17
CLKA
Name
Port A Data
Port A Almost-Empty
Flag
Port B Almost-Empty
Flag
Port A Almost-Full
Flag
Port C Almost-Full
Flag
Port B Data.
Port-C Data
Port A Clock
I/O
I/O
O
O
O
O
O
I
I
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit
words in FIFO2 is less than or equal to the value in the offset register, X.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit
words in FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty
locations in FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of
36-bit empty locations in FIFO2 is less than or equal to the value in the offset register, X.
18-bit output data port for side B.
18-bit input data port for side C.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB and CLKC.
EFA, FFA, AFA,
and
AEA
are synchronized
to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data read from port B and can be asynchronous
or coincident to CLKA and CLKC. Port B byte swapping and data port sizing operations are also
synchronous to the LOW-to-HIGH transition of CLKB.
EFB
and
AEB
are synchronized to the
LOW-to-HIGH transition of CLKB.
CLKC is a continuous clock that synchronizes all data written to port C and can be asynchronous
or coincident to CLKA and CLKC.
FFC
and
AFC
are synchronized to the LOW-to-HIGH transition
of CLKC.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
is LOW, FIFO2 is empty,
and reads from its memory are disabled. Data can be read from FIFO2 to the output register
when
EFA
is HIGH.
EFA
is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
is LOW, the FIFO1 is
empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when
EFB
is HIGH.
EFB
is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is LOW, FIFO1 is full,
and writes to its memory are disabled.
FFA
is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFC
is synchronized to the LOW-to-HIGH transition of CLKC. When
FFC
is LOW, FIFO2 is full,
and writes to its memory are disabled.
FFC
is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKC after reset.
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag offset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW. Bytes are organized as
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as
the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is
setup by having W/RA LOW, and PGA HIGH, the
PEFA
flag is forced HIGH regardless of the
A0-A35 inputs.
CLKB
Port B Clock
I
CLKC
Port-C Clock
I
CSA
EFA
Port A Chip Select
Port A Empty Flag
I
O
EFB
Port B Empty Flag
O
ENA
FFA
FFC
Port A Enable
Port A Full Flag
I
O
Port C Full Flag
O
FS1, FS0
ODD/
EVEN
PEFA
Flag-Offset Selects
Odd/Even Parity
Select
Port A Parity Error
Flag
I
I
O
4
IDT723616 CMOS TRIPLE BUS SyncFIFO™ WITH
™
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
PEFC
Name
Port C Parity Error
Flag
I/O
O
Description
When any valid byte applied to terminals B0-B17 fails parity,
PEFC
is LOW. Bytes are organized
as B0-B8 and B9-B17 with the most significant bit of each byte serving as the parity bit. A byte
is valid when it is used by the bus size selected for Port C. The type of parity checked is
determined by the state of the ODD/
EVEN
input.
The parity trees used to check the B0-B17 inputs are shared by the mail 1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having WENC LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the
PEFC
flag is forced HIGH
regardless of the state of the B0-B17 inputs.
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8 and B9-B17. The
generated parity bits are output in the most significant bit of each byte.
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on port B.
To reset the device, four LOW-to-HIGH transitions of CLKA, four LOW-to-HIGH transitions of CLKB,
and four LOW-to-HIGH transitions of CLKC must occur while
RST
is LOW. This sets the
AFA
and
AFC
flags HIGH and the
EFA, EFB, AEA, AEB, FFA,
and
FFC
flags LOW. The LOW-to-HIGH
transition of
RST
latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-
Empty flag offsets.
The levels on these inputs determine the bus size for ports B and C . These levels must be
stable before Master Reset and must remain static for the duration of FIFO operation. Either
a word or a byte size may be selected for both ports B and C together; the ports cannot be
configured independently.
The levels on these inputs select one of four modes of byte-order swapping for Port B. These levels
must be stable before Master Reset and must remain static for the duration of FIFO operation. The
four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is
possible with any bus size selection.
The levels on these inputs select one of four modes of byte-order swapping for Port C. These levels
must be stable before Master Reset and must remain static for the duration of FIFO operation. The
four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is
possible with any bus size selection.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
A HIGH selects a Port C write operation for a LOW-to-HIGH transition of CLKC.
PGA
Port A Parity
Generation
Port B Parity
Generation
Port B Read Enable
Reset
I
PGB
I
RENB
RST
I
I
SIZ0, SIZ1
Bus Size Select
(Ports B and C)
I
SWB0
SWB1
Port B Byte Swap
I
SWC0
Port C Byte Swap
I
W/RA
WENC
Port A Write/Read
Select
Port C Write Enable
I
I
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