F
LASH
370i™ ISR™
CPLD Family
UltraLogic™ High-Density Flash CPLDs
Features
• Flash In-System Reprogrammable (ISR™) CMOS
CPLDs
— Combines on board reprogramming with pinout flex-
ibility and a simple timing model
— Design changes don’t cause pinout or timing chang-
es
— JTAG interface
• High density
— 32–128 macrocells
— 32–128 I/O pins
•
•
•
•
— Multiple clock pins
Fully PCI compliant
Bus Hold capabilities on all I/Os and dedicated inputs
3.3-V or 5.0-V I/O operation on all devices
High speed
— t
PD
= 8.5–10 ns
— t
S
= 5–7 ns
— t
CO
= 6–7 ns
• Fast Programmable Interconnect Matrix (PIM)
— Uniform predictable delay, independent of routing
• Intelligent product term allocator
— 0–16 product terms to any macrocell
— Provides product term steering on an individual ba-
sis
— Provides product term sharing among local macro-
cells
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• Flexible clocking
— 2–4 clock pins per device
— Clock polarity control
• Security bit and user ID supported
• Packages
— 44–160 pins
— PLCC, CLCC, PGA, CQFP, and TQFP packages
General Description
The F
LASH
370i™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
performance. Each member of the family is designed with Cy-
press’s state-of-the-art 0.65-micron Flash technology.
All of the UltraLogic F
LASH
370i devices are electrically eras-
able and In-System Reprogrammable (ISR), which simplifies
both design and manufacturing flows, thereby reducing costs.
Because of the superior routability of the F
LASH
370i devices,
ISR allows users to change existing logic designs without
changing pinout assignments or timing. The Cypress ISR
function is implemented through a JTAG serial interface. Data
is shifted in and out through the SDI and SDO pins, respec-
tively. The ISR interface is enabled from the programming volt-
age pin (ISR
EN
). The entire family is fully compliant with the
PCI Local Bus specification, meeting all the electrical and tim-
ing requirements. Also, the entire family features bus-hold ca-
pabilities on all I/Os and dedicated inputs. Additionally, the en-
tire family is security bit and user ID supported (when the
security bit is programmed, all locations cannot be verified).
F
LASH
370i Selection Guide
Device
371i
372i
373i
374i
375i
Pins
44
44
84/100
84/100
160
Macrocells
32
64
64
128
128
Dedicated
Inputs
5
5
5
5
5
I/O Pins
32
32
64
64
128
Flip-Flops
44
76
76
140
140
Speed (t
PD
)
8.5
10
10
10
10
Speed (f
MAX
)
143
125
125
125
125
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 20, 2000
F
LASH
370i™ ISR™
CPLD Family
General Description
(continued)
The F
LASH
370i family is designed to bring the flexibility, ease
of use and performance of the 22V10 to high-density CPLDs.
The architecture is based on a number of logic blocks that are
connected by a Programmable Interconnect Matrix (PIM).
Each logic block features its own product term array, product
term allocator array, and 16 macrocells. The PIM distributes
signals from the logic block outputs and all input pins to the
logic block inputs.
The family features a wide variety of densities and pin counts
to choose from. At each density there are two packaging op-
tions to choose from—one that is I/O intensive and another
that is register intensive. For example, the CY7C374i and
CY7C375i both feature 128 macrocells. On the CY7C374i,
available in 84-pin packages, half of the macrocells are buried.
On the CY7C375i, available in 160-pin packages, all of the
macrocells are fed to I/O pins.
Figure 1
shows a block diagram
of the CY7C374i/5i.
propagation delay through the PIM is transparent to the user.
Signals from any pin or any logic block can be routed to any or
all logic blocks.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic block(s). Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also im-
proves the routing capacity of the F
LASH
370i family.
An important feature of the PIM is simple timing. The propaga-
tion delay through the PIM is accounted for in the timing spec-
ifications for each device. There is no additional delay for trav-
eling through the PIM. In fact, all inputs travel through the PIM.
Likewise, there are no route-dependent timing parameters on
the F
LASH
370i devices. The worst-case PIM delays are incor-
porated in all appropriate F
LASH
370i specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary.
Warp™
and third-party development packages
automatically route designs for the F
LASH
370i family in a mat-
ter of minutes. Finally, the rich routing resources of the
F
LASH
370i family accommodate last minute logic changes
while maintaining fixed pin assignments.
Functional Description
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM is an extremely ro-
bust interconnect that avoids fitting and density limitations.
Routing is automatically accomplished by software and the
Logic Block Diagram
CLOCK
INPUTS INPUTS
1
INPUT
MACROCELL
4
8/16 I/Os
LOGIC
BLOCK
36
16
36
16
36
16
36
16
PIM
4
INPUT/CLOCK
MACROCELLS
4
36
16
36
16
36
16
36
16
LOGIC
BLOCK
8/16 I/Os
A
LOGIC
BLOCK
H
LOGIC
BLOCK
8/16 I/Os
8/16 I/Os
B
LOGIC
BLOCK
G
LOGIC
BLOCK
8/16 I/Os
C
LOGIC
BLOCK
F
LOGIC
BLOCK
8/16 I/Os
8/16 I/Os
8/16 I/Os
7C3740i-1
D
32/64
E
32/64
Figure 1. CY7C374i/5i Block Diagram
2
F
LASH
370i™ ISR™
CPLD Family
.
0–16
2
PRODUCT
TERMS
MACRO-
CELL
1
6
0–16
PRODUCT
TERMS
MACRO-
CELL
8
FROM
PIM
36
72 x 86
PRODUCT TERM
ARRAY
80
PRODUCT
TERM
ALLOCATOR
0–16
PRODUCT
MACRO-
TERMS
CELL
9
0–16
PRODUCT
MACRO-
TERMS
CELL
16
TO
PIM
16
16
2
I/O
CELL
1
2
I/O
CELL
8
I/O
CELL
9
I/O
CELL
16
flash370i–2
Figure 2. Logic Block for CY7C371i, CY7C373i, and CY7C375i (I/O Intensive)
3
F
LASH
370i™ ISR™
CPLD Family
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
2
MACRO-
CELL
1
MACRO-
CELL
2
I/O
CELL
1
2
2
6
to cells
3,5,7
FROM
PIM
36
72 x 86
PRODUCT TERM
ARRAY
80
PRODUCT
TERM
ALLOCATOR
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
MACRO-
CELL
9
MACRO-
CELL
16
I/O
CELL
9
TO
PIM
to cells
11,13,15
16
8
flash370i–3
Figure 3. Logic Block for CY7C372i and CY7C374i (Register Intensive)
Logic Block
The logic block is the basic building block of the F
LASH
370i
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used.
There are two types of logic blocks in the F
LASH
370i family. The
first type features an equal number (16) of I/O cells and mac-
rocells and is shown in
Figure 2.
This architecture is best for
I/O-intensive applications. The second type of logic block fea-
tures a buried macrocell along with each I/O macrocell. In oth-
er words, in each logic block, there are eight macrocells that
are connected to I/O cells and eight macrocells that are only
internally fed back to the PIM. This organization is designed
for register-intensive applications and is displayed in
Figure 3.
Note that at each F
LASH
370i density (except the 32-macrocell
CY7C371i), an I/O intensive and a register-intensive device is
available.
Product Term Array
Each logic block features a 72 x 86 programmable product
term array. This array is fed with 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 86 product
terms in the array can be created from any of the 72 inputs.
Of the 86 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Four of the remaining six
product terms in the logic block are output enable (OE) product
terms. Each of the OE product terms controls up to eight of the
16 macrocells and is selectable on an individual macrocell ba-
sis. In other words, each I/O cell can select between one of two
OE product terms to control the output buffer. The first two of
these four OE product terms are available to the upper half of
the I/O macrocells in a logic block. The other two OE product
terms are available to the lower half of the I/O macrocells in a
logic block. The final two product terms in each logic block are
dedicated asynchronous set and asynchronous reset product
terms.
Product Term Allocator
Through the product term allocator, software automatically dis-
tributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator pro-
vides two important capabilities without affecting performance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On F
LASH
370i devices, prod-
uct terms are steered on an individual basis. Any number be-
tween 0 and 16 product terms can be steered to any macrocell.
Note that 0 product terms is useful in cases where a particular
macrocell is unused or used as an input register.
4
F
LASH
370i™ ISR™
CPLD Family
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than one
output has one or more product terms in its equation that are
common to other outputs, those product terms are only pro-
grammed once. The F
LASH
370i product term allocator allows
sharing across groups of four output macrocells in a variable
fashion. The software automatically takes advantage of this ca-
pability—the user does not have to intervene. Note that greater
usable density can often be achieved if the user “floats” the pin
assignment. This allows the compiler to group macrocells that
have common product terms adjacently.
Note that neither product term sharing nor product term steering
have any effect on the speed of the product. All worst-case
steering and sharing configurations have been incorporated in
the timing specifications for the F
LASH
370i devices.
F
LASH
370i Macrocell
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells depend-
ing on the device used.
Figure 4
illustrates the architecture of
the I/O macrocell. The macrocell features a register that can be
configured as combinatorial, a D flip-flop, a T flip-flop, or a lev-
el-triggered latch.
The register can be asynchronously set or asynchronously reset
at the logic block level with the separate set and reset product
terms. Each of these product terms features programmable po-
larity. This allows the registers to be set or reset based on an
AND expression or an OR expression.
Clocking of the register is very flexible. Depending on the de-
vice, either two or four global synchronous clocks are available
to clock the register. Furthermore, each clock features program-
mable polarity so that registers can be triggered on falling as
well as rising edges (see the Dedicated/Clock Inputs section).
Clock polarity is chosen at the logic block level.
At the output of the macrocell, a polarity control mux is available
to select active LOW or active HIGH signals. This has the added
advantage of allowing significant logic reduction to occur in
many applications.
The F
LASH
370i macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the mac-
rocell is buried (fed back internally only), the associated I/O pin
can still be used as an input.
Buried Macrocell
Some of the devices in the F
LASH
370i family feature additional
macrocells that do not feed individual I/O pins
Figure 5.
displays
the architecture of the I/O and buried macrocells for these de-
vices. The I/O macrocell is identical to the I/O macrocell for de-
vices without buried macrocells.
The buried macrocell is very similar to the I/O macrocell. Again,
it includes a register that can be configured as combinatorial, a
D flip-flop, a T flip-flop, or a latch. The clock for this register has
the same options as described for the I/O macrocell. The prima-
ry difference between the I/O macrocell and the buried macro-
cell is that the buried macrocell does not have the ability to out-
put data directly to an I/O pin.
One additional difference on the buried macrocell is the addition
of input register capability. The buried macrocell can be config-
ured to act as an input register (D-type or latch) whose input
comes from the I/O pin associated with the neighboring macro-
cell. The output of all buried macrocells is sent directly to the
PIM regardless of its configuration.
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
