Preliminary
74LCXZ163245 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs (Preliminary)
May 2001
Revised May 2001
74LCXZ163245
16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs (Preliminary)
General Description
The 74LCXZ163245 is a dual supply, 16-bit, translating
transceiver that is designed for two-way asynchronous
communication between busses at different supply volt-
ages. This device is suited for PCMCIA and other real-time
configurable I/O applications that utilize mixed power sup-
plies.
The 74LCXZ163245 is designed to Power-Up and Power-
Down into a High Impedance state (outputs disabled). The
feature eliminates the need to power-up in a specific
sequence to avoid drawing excessive current.
The A Port interfaces with the higher voltage bus (3.0V to
5.5V), and the B Port interfaces with the lower voltage bus
(2.3V to 3.6V). This dual supply design allows for transla-
tion from low voltage busses (2.3V to 3.6V) to busses at a
higher potential, up to 5.5V. The 74LCXZ163245 is
intended to be used in applications where the A Port is con-
nected to the PCMCIA card slots, and the B Port is con-
nected to the 3.0V host system.
Furthermore, when both OE’s are HIGH, the A Port I/O pins
are disabled, and both A Port I/O connections and A Port
V
CC
are allowed to float. This feature permits PCMCIA
cards to be inserted and removed during normal operation.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports; Receive (active-LOW) enables data from
B Ports to A Ports. The Output Enable (OE
1
, OE
2
) inputs,
when HIGH, disable their associated ports by placing the
I/Os in HIGH-Z condition. The 74LCXZ163245 is designed
so that the control pins (T/R
n
, OE
n
) are powered by V
CCB
,
so that V
CCA
may be removed when the I/Os are disabled.
The 74LCXZ163245 is suitable for mixed voltage applica-
tions such as notebook computers using a 3.3V CPU and
5.0V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s
Bidirectional interface between 3V busses and
5V busses
s
Supports live insertion and withdrawal (Note 1)
s
Outputs source/sink up to 24 mA
s
Uses patented Quiet Series
noise/EMI reduction
circuitry
s
Functionally compatible with the 74 series 16245
s
Port A I/O may be disabled by use of OE
n
or removal of
A Port V
CC
s
Port A V
CC
may be removed when OE
n
is used to
disable I/O’s
s
Port A V
CC
removal may occur coincident with rising
edge of OE
n
s
Configurable as one 16-bit or two 8-bit transceivers
s
Unrestricted power-up sequencing
Note 1:
To ensure the high impedance state during power up or down OE
should be tied to V
CC
through a pull-up resistor; the minimum value of the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCXZ163245MTD
Package
Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500364
www.fairchildsemi.com
Preliminary
74LCXZ163245
Logic Symbol
Pin Descriptions
Pin Names
OE
n
T/R
n
A
0
–A
15
B
0
–B
15
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Connection Diagram
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
T/R
2
L
H
X
Outputs
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH-Z State on A
8
–A
15
, B
8
–B
15
T/R
1
L
H
X
Outputs
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH Z State on A
0
–A
7
, B
0
–B
7
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
LCXZ163245 Translator Power Up Note
The LCXZ163245 Translator is designed with two separate
V
CC
power rails. V
CCA
is the higher potential rail, operating
at 3.0 to 5.5 volts, and V
CCB
is the lower potential rail, oper-
ating at 2.3 to 3.6 volts. The control pins of the device
(OE
n
, T/R
n
) are supplied by the V
CCB
rail.
The LCXZ163245 will remain in high impedance mode
(outputs are disabled) when V
CCA
and/or V
CCB
is between
0 volts and 1.5 volts during power up. Placing the outputs
in a high impedance (Z) state prevents intermittent low
impedance loading or glitching in bus oriented applications.
To ensure the high impedance state during power up
beyond a V
CC
of 1.5V and also during power down, the
OE
n
pin should be tied to V
CCB
through a pull up resistor.
The minimum value of this resistor is determined by the
current-sourcing capability of the device driving the OE
n
pin.
Logic Diagrams
Note:
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Preliminary
74LCXZ163245
Absolute Maximum Ratings
(Note 2)
Symbol
Parameter
Value
Conditions
Units
V
OE, T/R Control Pins
Outputs 3-STATE
A Outputs in HIGH or LOW State (Note 3)
B Outputs in HIGH or LOW State (Note 3)
V
I
<
GND (OE, T/R)
V
O
<
GND
V
O
>
V
CC
mA
mA
mA
mA
mA
V
V
V
CCA
, V
CCB
Supply Voltage
V
I
V
I/O
DC Input Voltage
DC Output Voltage
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to V
CCA
+
0.5
−
0.5 to V
CCB
+
0.5
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
DC Input Diode Current
DC Output Diode Current
DC Output Source or Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
−
50
−
50
±
50
±
50
±
100
±
100
−
65 to
+
150
°
C
Recommended Operating Conditions
(Note 4)
Symbol
V
CC
V
I
V
I/O
Supply Voltage
Parameter
V
CCB
V
CCA
Input Voltage @ OE, T/R
Output Voltage
A
n
HIGH or LOW State
B
n
HIGH or LOW State
3-STATE
T
A
Free Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V - 2.0V, V
CCB
=
2.3V - 3.6V, V
CCA
=
4.5V - 5.5V
Min
2.3
3.0
0
0
0
0
Max
3.6
5.5
5.5
V
CCA
V
CCB
5.5
85
10
V
Units
V
V
−
40
°
C
ns/V
∆
t/
∆
V
Note 2:
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Unused inputs or I/O’s must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IHA
Parameter
Minimum HIGH
Level Input
Voltage
V
IHB
B
n
OE
T/R
V
ILA
Maximum LOW
Level Input
Voltage
V
ILB
B
n
OE
T/R
A
n
A
n
V
CCB
(V)
2.3
3.0
3.6
2.3
3.0
3.6
2.7
3.0
3.6
2.7
3.0
3.6
V
CCA
(V)
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
T
A
= −40°C
to
+85°C
Min
2.0
2.0
2.0
1.7
2.0
2.0
0.8
0.8
0.8
0.7
0.8
0.8
V
V
Max
Units
Conditions
3
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