74LCX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED:
f
MAX
= 150 MHz (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX74MTR
74LCX74TTR
DESCRIPTION
The 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
Figure 1: Pin Connection And IEC Logic Symbols
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
September 2004
Rev. 7
1/14
74LCX74
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1CLR, 2CLR
1D, 2D
1CK, 2CK
1PR, 2PR
1Q, 2Q
1Q, 2Q
GND
V
CC
NAME AND FUNCTION
Asynchronous Reset - Direct Input
Data Inputs
Clock Input (LOW to HIGH, Edge Triggered)
Asynchronous Set - Direct Input
True Flip-Flop Outputs
Complement Flip-Flop Outputs
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
CLR
L
H
L
H
H
H
X : Don’t Care
OUTPUTS
FUNCTION
D
X
X
X
L
H
X
CK
X
X
X
Q
L
H
H
L
H
Q
n
Q
H
L
H
H
L
Q
n
NO CHANGE
CLEAR
PRESET
PR
H
L
L
H
H
H
2/14
74LCX74
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (V
CC
= 0V)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (V
CC
= 0V)
Output Voltage (High or Low State)
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V)
Operating Temperature
Input Rise and Fall Time (note 2)
Parameter
Value
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
°C
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
3/14
74LCX74
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
-40 to 85 °C
Min.
2.0
2.7 to 3.6
0.8
2.7 to 3.6
2.7
3.0
V
OL
Low Level Output
Voltage
2.7 to 3.6
2.7
3.0
I
I
I
off
I
CC
∆I
CC
Input Leakage
Current
Power Off Leakage
Current
Quiescent Supply
Current
I
CC
incr. per Input
2.7 to 3.6
0
2.7 to 3.6
2.7 to 3.6
I
O
=-100
µA
I
O
=-12 mA
I
O
=-18 mA
I
O
=-24 mA
I
O
=100
µA
I
O
=12 mA
I
O
=16 mA
I
O
=24 mA
V
I
= 0 to 5.5V
V
I
or V
O
= 5.5V
V
I
= V
CC
or GND
V
I
or V
O
= 3.6 to 5.5V
V
IH
= V
CC
- 0.6V
V
CC
-0.2
2.2
2.4
2.2
0.2
0.4
0.4
0.55
±
5
10
10
±
10
500
V
CC
-0.2
2.2
2.4
2.2
0.2
0.4
0.4
0.55
±
5
10
10
±
10
500
µA
µA
µA
µA
V
V
0.8
V
Max.
Value
-55 to 125 °C
Min.
2.0
Max.
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
Value
T
A
= 25 °C
Min.
Typ.
0.8
-0.8
Max.
V
Unit
V
OLP
V
OLV
Dynamic Low Level Quiet
Output (note 1)
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
4/14
74LCX74
Table 8: AC Electrical Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
C
L
(pF)
50
50
50
50
R
L
(Ω)
500
500
500
500
t
s
=
t
r
(ns)
2.5
2.5
2.5
2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
1.5
2.5
2.5
1.5
1.5
3.0
3.0
0
0
150
1.0
Max.
8.0
7.0
8.0
7.0
Value
-55 to 125 °C
Min.
1.5
1.5
1.5
1.5
3.5
3.5
1.5
1.5
4.0
4.0
0
0
150
1.0
Max.
9.2
8.0
9.2
8.0
ns
ns
ns
ns
Unit
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
Time (CK to Q or Q)
Propagation Delay
Time (PR or CLR to
Q or Q)
Setup Time, HIGH or
LOW level D to CK
Hold Time, HIGH or
LOW level D to CK
CK Pulse Width,
HIGH or LOW
PR or CLR Pulse
Width, LOW
Recovery Time PR
or CLR to CK
Clock Pulse
Frequency
Output To Output
Skew Time (note1,
2)
t
S
t
h
t
W
50
500
2.5
ns
t
rec
f
MAX
t
OSLH
t
OSHL
50
50
50
500
500
500
2.5
2.5
2.5
ns
MHz
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
Value
T
A
= 25 °C
Min.
Typ.
6
40
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Flip-Flop)
5/14
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