74LCX652
LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER
WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 7.0 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 652
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LCX652M1R
T&R
74LCX652RM13TR
74LCX652TTR
DESCRIPTION
The 74LCX652 is a low voltage CMOS OCTAL
BUS
TRANSCEIVER
AND
REGISTER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for both inputs and outputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
storage registers. Enable (GAB) and (GBA) pins
are provided to control the transceiver functions.
Select AB and Select BA control pins are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time,
and a high selects stored data.
Data on the A or B bus, or both, can be stored in
the internal D flip-flop by low to high transitions at
the appropriate clock pins (CAB or CBA)
regardless of the select or enable control pins.
When select AB and select BA are in the real-time
transfer mode, it is also possible to store data
September 2001
1/13
M74LCX652
without using the internal D-type flip-flops by
simultaneously enabling GAB or GBA. In this
configuration each output reinforces its input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN DESCRIPTION
PIN No
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
12
24
SYMBOL
CLOCK AB (CAB)
SELECT AB (SAB)
GAB
A1 to A8
B1 to B8
GBA
SELECT BA (SBA)
CLOCK BA (CBA)
GND
V
CC
NAME AND FUNCTION
A to B Clock Input (LOW to HIGH,
Edge-Triggered)
Select A to B Source Input
Direction Control Input
A Data Inputs/Outputs
B Data Inputs/Outputs
Output Enable Input (Active LOW)
Select B to A Source Input
B to A Clock Input (LOW to HIGH,
Edge Triggered)
Ground (0V)
Positive Supply Voltage
2/13
M74LCX652
TRUTH TABLE
GAB GBA CAB CBA SAB SBA
X
L
H
X
X
INPUTS
OUTPUTS
L
H
L
INPUTS
INPUTS
L
H
L
X
X
X
A
INPUTS
Z
B
INPUTS
Z
FUNCTION
Both the A bus and the B bus are inputs
The Output functions of the A and B bus are disabled
Both the A and B bus are used for inputs to the internal
flip-flops. Data at the bus will be stored on low to high
transition of the clock inputs.
The A bus are outputs and the B bus are inputs
The data at the B bus are displayed at the A bus
X*
X*
L
L
X*
X*
X
X
X
L
L
H
H
X
X
X
X
X*
X*
L
L
H
H
H
X
X
X
X
X
H
H
X
X*
X*
X*
H
L
X
X
H
H
The data at the B bus are displayed at the A bus. The
data of the B bus are stored to internal flip-flop on low
H
H
to high transition of the clock pulse
The data stored to the internal flip-flop are displayed at
Qn
X
the A bus.
L
L
The data at the B bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
H
H
of the internal flip-flops output directly to the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus are outputs.
L
L
The data at the A bus are displayed at the B bus
H
H
L
L
The data at the A bus are displayed at the B bus. The
data of the A bus are stored to the internal flip-flop on
H
H
low to high transition of the clock pulse.
The data stored to the internal flip-flops are displayed
X
Qn
at the B bus
L
L
The data at the A bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
H
H
of the internal flip-flops output directly to the B bus.
OUTPUTS OUTPUTS Both the A bus and the B bus are outputs
The data stored to the internal flip-flops are displayed
Qn
Qn
at the A and B bus respectively.
X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
3/13
M74LCX652
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
4/13
M74LCX652
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (OFF State)
Output Voltage (High or Low State)
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V)
Operating Temperature
Input Rise and Fall Time (note 2)
Parameter
Value
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
°C
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
5/13
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