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74LCX652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
February 1994
Revised March 2001
74LCX652
Low Voltage Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The LCX652 is designed for low voltage (2.5V or 3.3V) V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V
−
3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
=
3.3V), 10
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX652WM
74LCX652MSA
74LCX652MTC
Package Number
M24B
MSA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
7
, B
0
–B
7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
© 2001 Fairchild Semiconductor Corporation
DS011998
www.fairchildsemi.com
74LCX652
Logic Symbols
IEEE/IEC
Truth Table
(Note 2)
Inputs
OEAB OEBA
L
L
X
H
L
L
L
L
H
H
H
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
CPBA
H or L
SAB
X
X
X
X
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X
L
H
X
X
H
Output
Output
Input
Output
Input
Input
Not Specified
Output
Output
Not Specified
Output
Input
Input
Input
Inputs/Outputs
A
0
thru A
7
Input
B
0
thru B
7
Input
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Operating Mode
H or L
X
X
X
H or L
X
X
X
H or L
H or L
H or L
H or L
Note 2:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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2
74LCX652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceiver and receiver.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
OEAB OEBA CPAB CPBA SAB SBA
H
H
X
X
L
X
Transfer Storage
Data to A or B
Storage
OEAB OEBA CPAB CPBA SAB SBA
H
L
H or L H or L
H
H
OEAB OEBA CPAB CPBA SAB SBA
X
L
L
H
X
H
X
X
X
X
X
X
X
X
3
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74LCX652
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
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