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74LCX14T

产品描述LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14, TSSOP-14
产品类别逻辑    逻辑   
文件大小55KB,共8页
制造商ST(意法半导体)
官网地址http://www.st.com/
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74LCX14T概述

LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14, TSSOP-14

74LCX14T规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP, TSSOP14,.25
针数14
Reach Compliance Codenot_compliant
系列LVC/LCX/Z
JESD-30 代码R-PDSO-G14
JESD-609代码e0
长度5 mm
负载电容(CL)50 pF
逻辑集成电路类型INVERTER
功能数量6
输入次数1
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP14,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
电源3.3 V
Prop。Delay @ Nom-Sup6.5 ns
传播延迟(tpd)6.5 ns
认证状态Not Qualified
施密特触发器YES
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度4.4 mm
Base Number Matches1

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®
74LCX14
LOW VOLTAGE CMOS HEX SCHMITT INVERTER
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED:
t
PD
= 6.5 ns (MAX.) at V
CC
= 3.0V
POWER-DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 14
LATCH-UP PERFORMANCE EXCEEDS 500mA
ESD PERFORMANCE:
HBM >2000V; MM > 200V
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LCX14M
74LCX14T
AC/ACT family, combined with a lower power
consumption.
Pin configuration and function are the same as
those of the LCX04 but the LCX14 has hysteresis
between the positive and negative input threshold
typically of 0.8V.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LCX14 is a low voltage CMOS HEX
SCHMITT INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to
5V signal enviroment for inputs.
It has same speed performance at 3.3V than 5V,
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/8

 
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