Differences Between IDT’s
RC4640/RC64474/RC64574
RISController Microprocessors
By Ian Ferguson
Technical Note
TN-46
Integrated Device Technology (IDT) manufacture a range of 64-bit RISC microprocessors that offer a
high degree of compatibility. The RC4640, RC64474 and the RC64574 all offer an external 32-bit address/
data system bus, whereas the RC4650, RC64475 and RC64575 all offer a 64-bit address/data bus option
for higher bandwidth.
The RC64574 and RC64575 are members of IDT’s RISCore5000 family, whereas the RC64474,
RC64475, RC4640 and RC4650 are members of the RISCore4000 family. The RISCore4000 family is
based on the MIPS III instruction set architecture (ISA), whereas the RISCore5000 products use the MIPS
IV ISA.
November 29, 2000:
In Software Issues section, subsection Processor ID, changed RC64574 Imp =
0x23 to RC64574 Imp = 0x15.
From a software point of view, there is no difference between a device with a 32-bit bus (such as the
RC4640) and one with a 64-bit bus (such as the RC4650). The selection on bus width is made at boot time
and is handled completely by hardware.
Although there have been a number of improvements introduced in the RISCore5000 processor core,
the only difference that will be noticed by the user is that the RISCore5000 core issues both an integer and
a floating point instruction in a single clock cycle. This only affects performance. From the software
programming model, no change is required.
In this document, the RC4640/RC4650 is referred to as the RC4640 since both are based on the same
die, the RC64474/RC64475 is referred to as the RC64474, and the RC64574/RC64575 is referred to as the
RC64574.
1999 Integrated Device Technology, Inc.
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Initial publication.
Both the RC4640 and RC64474 are offered as 3.3V devices, while the RC64574 is offered as a 2.5V
device. The voltage to all Vcc pins must be selected as 2.5V for the RC64574 RISController. Note that the
IO pins of the RC64574 are 3.3V compatible, so the RC64574 will interface directly to 3.3V logic on the
printed circuit board (PCB).
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November 29, 2000
DSC 5915
Technical Note TN-46
JTAG
The RC64474 and RC64574 include a JTAG port for board-level test. This is not supported on the
RC4640. The JTAG pins should not be exercised if the RC4640 is fitted. The table below shows how the
pins assigned for the JTAG interface should be handled if a RC4640 is present in the system.
.
JR_Vcc
(JTag enable)
TDI
(JTAG DataIn)
TDO
(JTAG DataOut)
TMS
(JTAG Command)
TRst*
(JTAG Reset)
TCK
(JTAG Clock)
JTAG32*
NC
Internal pull-down disables in existing RC4640/50 systems
JR_Vcc overrides JTAG function
Output is tri-stated by JR_Vcc
JR_Vcc overrides JTAG function
JR_Vcc overrides JTAG function
JR_Vcc overrides JTAG function
Since JR_Vcc overrides JTAG, the selection doesn’t mat-
ter
Vss
Vss
Vss
Vss
Vss
NC
Write mode
The RC64474 and RC64574 include a new write mode to simplify interfacing to SDRAM. The default is
for this feature to be disabled, thus maintaining compatibility with the RC4640, but it can be selected at boot
time. This feature is not supported on the RC4640.
Processor ID
The processor ID register bits are defined as follows:
Bits 31..16 – defined as zero
Bits 15..8 – implementation number (defines which CPU)
Bits 7..0 – revision number of device.
RC64574 Imp = 0x15
RC64474 Imp = 0x30
RC4640 Imp = 0x22
This value is hardwired in the register. The code needs to be modified to reflect the new expected value
when reading the Process ID Register.
Cache Size
For all 64-bit RISControllers, the size of the instruction in a particular component is equal to the size of
the data cache. For the RC64574, the size of each is 32kB, for the RC64474 each is 16 kB, and for the
RC4640 each is 8kB. For all 64-bit RISControllers, the caches are 2 way set associative. The differing
cache sizes should only affect the cache initialization and cache flushing routines.
Cache Locking
The RC4640 and RC64474 provide a cache locking mechanism, allowing set A of either or of both the
instruction cache or data cache to be locked. The RC64574 RISController provides the user more control
over the areas of the primary caches that are locked. Specifically, the locking mechanism is enabled/
disabled on a per-line basis. The bits used for locking the cache are the same in all processors (bits 23 and
24 of status register). The process of unlocking the cache, however, is quite different – in the RC4640 and
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November 29, 2000
Technical Note TN-46
RC64474, the cache is unlocked by clearing the respective IL or DL bit. In the RC64574 clearing this bit
stops any further lines from being locked, but leaves those lines that are already locked unchanged. Cache
ops are required to unlock cache lines in the RC64574.
Interrupt Vector
The RC64474 RISController does not implement the optional interrupts exception vector location at
0x80000200 (if the “BEV” bit is set to 0) or at 0xBFC00400 (if the “BEV” bit is set to 1) that is implemented
by the RC4640. This optional exception vector is enabled through the CP0 Cause Register bit 23 (Cause.IV
bit in the RC4640). This bit is reserved in the case of RC64474.
There are two main areas of difference between the MIPS instruction sets which result in some addi-
tional instructions being present in the RC64574 compared to the RISCore4000 product family.
The first difference is that MIPS IV includes four conditional move instructions. These instructions move
the contents of one CPU general register to another based on whether a particular criteria related to a value
in a third register is met (for example, whether it is zero). These instructions are therefore included in the
RC64574 RISController. Applications running on RC4640 and RC64474 RISControllers attempting to use
this instruction will cause a reserved instruction exception to be issued.
The second difference relates to four instructions included to manipulate data between memory and
floating point registers. Specifically, MIPS IV supports the capability to load and store a word or double word
from/to a floating point register to/from a memory location. Applications running on RC4640 and RC64474
RISControllers attempting to use this instruction will cause a reserved instruction exception to be issued.
The RC4640 and the RC64574 have Iwatch and Dwatch registers while the RC64474 does not have
these registers. Accessing these registers in the RC64474 will result in undefined values.
The RC64474 and RC64574 both implement an MMU with 48 entry TLB while the RC4640 uses two
"base-bound" registers that act as a "mini" TLB. The RC64474 and RC64574 TLBs hold 48 entries
providing mapping for 48 odd/even page pairs with page sizes varying from 4kbytes to 16Mbytes. There-
fore, if software is using mapped space, the code to initialize and manipulate the “base-bound” registers on
the RC4640 needs to be modified to support the 48-entry TLB on the RC64474 and RC64574.
The RC64474 and the RC64574 do not include the "CAlg Register" that is implemented on the RC4640.
The CAlg Register is most often used in conjunction with the base-bound register to specify the cache
attribute of every memory region on the RC4640. This mechanism is accomplished by using the TLB on the
RC64474 and RC64574.
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MAD, MADU, and MUL instructions are part of the instruction set for the RC4640, but are not supported
in the RC64474. The behavior of the RC64474 is undefined if these instructions are executed (the
RC64474 might take a "reserved instruction exception").
In addition to the MAD, MADU, and MUL instructions included on the RC4640, the RC64574 includes
MSUB, CLO, CLZ instructions. The behavior of the RC64474 or RC4640 is undefined if these instructions
additional instructions are executed (the processors might take a "reserved instruction exception").
The RC64574 also includes a “fast multiply” mode. With this selected the multiplier operates with the
same repeat rate and latency as the RC4640 and the RC64474 (in terms of clock cycles). This feature is
guaranteed for RC64574 pipeline clock frequencies up to 250MHz. In order to achieve the highest clock
frequencies, however a slower rate must be selected in the RC64574, which will result in different multiply
timings.
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November 29, 2000
Technical Note TN-46
The RC4640 has only a single precision floating point unit, whereas the RC64574 and the RC64474
have double precision units. Double precision floating point software would need to be provided for a
RC4640-based system, if this level of code portability is required.
The RC4640 uses only 32-bit address lines internally, while the RC64474 and RC64574 use 64-bit
address lines internally. In most cases, this is totally transparent to the code since the RC64474 and
RC64574 will automatically sign extend 32-bit values into 64-bit values to maintain the same program
behavior as the RC4640. However, special care must be applied when migrating code from the RC4640 to
the RC64474 or RC64574, especially code segments that manipulate data to generate addresses using the
“load unsigned” (lwu, lbu, etc.) instructions.
For example, using the “load-word-unsigned” instruction in the RC4640 will load a value into a register.
When this value is later used as an address source, the right address will be generated by the RC4640. In
contrast, when this instruction is used in the RC64474 or RC64574, the upper 32-bit contents of the 64-bit
register become zeros when loading the value in a 64-bit register. When this register is later used as an
address source, a bus error exception will be generated if the most significant bit in the lower 32-bits of the
register is equal to 1.
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November 29, 2000
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