RISCore
TM
32300 Family
Integrated Processor
79RC32332
Features
RC32300 32-bit Microprocessor
– Up to 133 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
◆
Local Bus Interface
– Up to 66 MHz operation
– 23-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
◆
Interrupt Controller simplifies exception management
◆
Four general purpose 32-bit timer/counters
◆
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
◆
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 256MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 256Mb SDRAM device depths
– Automatic refresh generation
◆
Serial Peripheral Interface (SPI) master mode interface
◆
UART Interface
– 16550 compatible UART
– Baud rate support up to 1.5M
◆
Memory & Peripheral Controller
– 6 banks, up to 8MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
◆
Block Diagram
EJTAG
In-Circuit Emulator Interface
RISCore 32300
Enhanced MIPS-II ISA
Integer CPU
RC5000
Compatible
CP0
32-page
TLB
Interrupt Control
Programmable I/O
32-bit Timers
SPI Control
DMA Control
Local
Memory/IO
Control
UART
IPBus
Bridge
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
Figure 1 RC32332 Block Diagram
IDT
Peripheral
Bus
SDRAM
Control
PCI Bridge
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
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79RC32332
4 DMA Channels
– 4 general purpose DMA, each with endianess swappers and
byte lane data alignment
– Supports scatter/gather, chaining via linked lists of records
– Supports memory-to-memory, memory-to-I/O, memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
– Supports unaligned transfers
– Supports burst transfers
– Programmable DMA bus transactions burst size
(up to 16 bytes)
◆
PCI Bus Interface
– 32-bit PCI, up to 50 MHz
– Revision 2.1 compatible
– Target or master
– Host or satellite
– Two slot PCI arbiter
– Serial EEPROM support, for loading configuration registers
◆
Off-the-shelf development tools
◆
JTAG Interface (IEEE Std. 1149.1 compatible)
◆
208 QFP Package
◆
3.3V operation with 5V compatible I/O
◆
EJTAG in-circuit emulator interface
◆
CPU Execution Core
The RC32332 integrates the RISCore 32300, the same CPU core
found in the award-winning RC32364 microprocessor.
The RISCore 32300 implements the Enhanced MIPS-II ISA. Thus, it
is upwardly compatible with applications written for a wide variety of
MIPS architecture processors, and it is kernel compatible with the
modern operating systems that support IDT’s 64-bit RISController
product family.
The RISCore 32300 was explicitly defined and designed for inte-
grated processor products such as the RC32332. Key attributes of the
execution core found within this product include:
◆
High-speed, 5-stage scalar pipeline executes to 133MHz. This
high performance enables the RC32332 to perform a variety of
performance intensive tasks, such as routing, DSP algorithms,
etc.
◆
32-bit architecture with enhancements of key capabilities. Thus,
the RC32332 can execute existing 32-bit programs, while
enabling designers to take advantage of recent advances in
CPU architecture.
◆
Count leading-zeroes/ones. These instructions are common to a
wide variety of tasks, including modem emulation, voice over IP
compression and decompression, etc.
◆
Cache PREFetch instruction support, including a specialized
form intended to help memory coherency. System programmers
can allocate and stage the use of memory bandwidth to achieve
maximum performance.
◆
8kB of 2-way set associative instruction cache
Device Overview
The IDT RC32332 device is an integrated processor based on the
RC32300 CPU core. This product incorporates a high-performance, low-
cost 32-bit CPU core with functionality common to a large number of
embedded applications. The RC32332 integrates these functions to
enable the use of low-cost PC commodity market memory and I/O
devices, allowing the aggressive price/performance characteristics of
the CPU to be realized quickly into low-cost systems.
Serial
Channel
RC32332
Integrated
Core
Controller
SDRAM
Programmable I/O
FLASH
Serial
EEPROM
Local I/O
32-bit, 33MHz PCI
Figure 2 RC32332 Based System Diagram
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79RC32332
◆
◆
◆
◆
2KB of 2-way set associative data cache, capable of write-back
and write-through operation.
Cache locking per line to speed real-time systems and critical
system functions
On-chip TLB to enable multi-tasking in modern operating
systems
EJTAG interface to enable sophisticated low-cost in-circuit
emulation.
PCI Bus Bridge
In order to leverage the wide availability of low-cost peripherals for
the PC market as well as to simplify the design of add-in functions, the
RC32332 integrates a full 32-bit PCI bus bridge. Key attributes of this
bridge include:
◆
50 MHz operation
◆
PCI revision 2.1 compliant
◆
Programmable address mappings between CPU/Local memory
and PCI memory and I/O
◆
On-chip PCI arbiter
◆
Extensive buffering allows PCI to operate concurrently with local
memory transfers
◆
Selectable byte-ordering swapper
◆
5V tolerant I/O.
Synchronous-DRAM Interface
The RC32332 integrates a SDRAM controller which provides direct
control of system SyncDRAM running at speeds to 66MHz.
Key capabilities of the SDRAM controller include:
◆
Direct control of 4 banks of SDRAM (up to 2 64-bit wide DIMMs)
◆
On-chip page comparators optimize access latency.
◆
Speeds to 66MHz
◆
Programmable address map.
◆
Supports 16, 64, 128, or 256Mb SDRAM devices
◆
Automatic refresh generation driven by on-chip timer
◆
Support for discrete devices, SODIMM, or DIMM modules.
Thus, systems can take advantage of the full range of commodity
memory that is available, enabling system optimization for cost, real-
estate, or other attributes.
On-Chip DMA Controller
To minimize CPU exception handling and maximize the efficiency of
system bandwidth, the RC32332 integrates a very sophisticated 4-
channel DMA controller on chip.
The RC32332 DMA controller is capable of:
◆
Chaining and scatter/gather support through the use of a
flexible, linked list of DMA transaction descriptors
◆
Capable of memory<->memory, memory<->I/O, and
PCI<->memory DMA
◆
Unaligned transfer support
◆
Byte, halfword, word, quadword DMA support.
Local Memory and I/O Controller
The local memory and I/O controller implements direct control of
external memory devices, including the boot ROM as well as other
memory areas, and also implements direct control of external periph-
erals.
The local memory controller is highly flexible, allowing a wide range
of devices to be directly controlled by the RC32332 processor. For
example, a system can be built using an 8-bit boot ROM, 16-bit FLASH
cards (possibly on PCMCIA), a 32-bit SRAM or dual-port memory, and a
variety of low-cost peripherals.
Key capabilities include:
◆
Direct control of EPROM, FLASH, RAM, and dual-port memories
◆
6 chip-select outputs, supporting up to 8MB per memory space
◆
Supports mixture of 8-, 16-, and 32-bit wide memory regions
◆
Flexible timing protocols allow direct control of a wide variety of
devices
◆
Programmable address map for 2 chip selects
◆
Automatic wait state generation.
On-Chip Peripherals
The RC32332 also integrates peripherals that are common to a wide
variety of embedded systems.
◆
Single 16550 compatible UART.
◆
SPI master mode interface for direct interface to EEPROM,
A/D, etc.
◆
Interrupt Controller to speed interrupt decode and management
◆
Four 32-bit on-chip Timer/Counters
◆
Programmable I/O module
Debug Support
To facilitate rapid time to market, the RC32332 provides extensive
support for system debug.
First and foremost, this product integrates an EJTAG in-circuit emula-
tion module, allowing a low-cost emulator to interoperate with programs
executing on the controller. By using an augmented JTAG interface, the
RC32332 is able to reuse the same low-cost emulators developed
around the RC32364 CPU.
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May 2, 2002
79RC32332
Secondly, the RC32332 implements additional reporting signals
intended to simplify the task of system debugging when using a logic
analyzer. This product allows the logic analyzer to differentiate transac-
tions initiated by DMA from those initiated by the CPU and further allows
CPU transactions to be sorted into instruction fetches vs. data fetches.
Finally, the RC32332 implements a full boundary scan capability,
allowing board manufacturing diagnostics and debug.
November 1, 2001:
Added Input Voltage Undershoot parameter and
2 footnotes to Table 10. Changed to DH package.
March 20, 2002:
In Local System Interface section of AC Timing
Characteristics table, changed values in Min column for last category of
signals (Tdoh3) from 2.5 to 1.5 for both speeds. In Table 8, PCI Drive
Output Pads, the Conditions for parameters V
OL
, V
OH
, V
IL
, and V
IH
were
changed to read Per PCI 2.1.
May 2, 2002:
Changed upper ambient temperature for commercial
uses back from +85° C to +70° C (changed erroneously from 70 to 85
on March 13, 2001). In Ambient Operating Temperature section of
Absolute Maximum Ratings table, specified that Ta refers to industrial
and changed 0° to 70° temperature range to -40° to +85° . Added
Reset State Status column to Table 1. Revised description of jtag_trst_n
in Table 1 and changed this pin to a pull-down instead of a pull-up.
Packaging
The RC32332 is packaged using a 208 Quad Flat Pack (QFP)
package.
Thermal Considerations
The RC32332 consumes less than 2.0 W peak power. The device is
guaranteed in an ambient temperature range of 0° to +70° C for
commercial temperature devices; -40° to +85° C for industrial tempera-
ture devices.
Revision History
November 15, 2000:
Initial publication.
December 12, 2000:
Changed Max values for cpu_masterclock
period in Table 5 and added footnote. In Table 1, added 2nd alternate
function for spi_mosi, spi_miso, spi_sck. In Table 11, added “2” in Alt
column for pins 186, 187, 188. In RC32332 Alternate Signal Functions
table, added pin names in Alt #2 column for pins 186, 187, 188.
January 4, 2001:
In Table 6 under Interrupt Handling, changed
Tdoh9 to Thld13 and moved the values for Tsu9 from the Max to the Min
column.
February 23, 2001:
In Table 1, changed alternate function for
uart_tx[0] from PIO[3] to PIO[1]. In Table 11, changed the number of
alternate pins for Pin 156 from 1 to 2. In Table 12, added PIO[7] to Alt #2
column for Pin 156 and changed PIO[3] to PIO[1] for Pin 207.
March 13, 2001:
Changed upper ambient temperature for industrial
and commercial uses from +70° C to +85° C.
June 7, 2001:
In the Clock Parameters table, added footnote 3 to
output_clk category and added NA to Min and Max columns. In Figure 3
(Reset Specification), enhanced signal line for cpu_masterclk. In Local
System Interface section of AC Timing Characteristics table, changed
values in Min column for last category of signals (Tdoh3) from 1.5 to 2.5
for both speeds. In SDRAM Controller section of same table, changed
values in Min column for last category of signals (9 signals) from 1 to 2.5
for both speeds.
September 14, 2001:
In the Reset category of Table 6: switched
mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10;
switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and
Thld22; moved ejtag_pcst[2:0] from Reset to Debug Interface category
under Tsu20 and Thld20.
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79RC32332
Pin Description Table
The following table lists the pins provided on the RC32332. Note that those pin names followed by “_n” are active-low signals. All external pull-ups
and pull-downs require
10 kΩ resistor.
Name
Type
Drive
Reset
Strength
State
Status Capability
Description
Local System Interface
mem_data[31:0]
mem_addr[22:2]
I/O
I/O
Z
[22:10] Z
[9:2] L
High
Local system data bus
Primary data bus for memory. I/O and SDRAM.
[22:16] Low
Memory Address Bus
These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During
[15:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transac-
tion type. The table below indicates how the memory write enable signals are used to address discreet
memory port width types.
Port Width
32-bit
16-bit
8-bit
Pin Signals
mem_we_n[3]
mem_we_n[3]
mem_we_n[2] mem_we_n[1]
mem_we_n[2]
mem_we_n[2]
mem_we_n[1]
mem_we_n[1]
Not Used (Driven
Low)
mem_addr[0]
mem_we_n[0]
mem_we_n[0]
mem_we_n[0]
Byte Low Write
Enable
Byte Write Enable
DMA (32-bit) mem_we_n[3]
Byte High Write Enable mem_addr[1]
Not Used (Driven High) mem_addr[1]
mem_addr[22] Alternate function: reset_boot_mode[1].
mem_addr[21] Alternate function: reset_boot_mode[0].
mem_addr[20] Alternate function: reset_pci_host_mode.
mem_addr[19] Alternate function: modebit [9].
mem_addr[18] Alternate function: modebit [8].
mem_addr[17] Alternate function: modebit [7].
mem_addr[15] Alternate function: sdram_addr[15].
mem_addr[14] Alternate function: sdram_addr[14].
mem_addr[13] Alternate function: sdram_addr[13].
mem_addr[11] Alternate function: sdram_addr[11].
mem_addr[10] Alternate function: sdram_addr[10].
mem_addr[9] Alternate function: sdram_addr[9].
mem_addr[8] Alternate function: sdram_addr[8].
mem_addr[7] Alternate function: sdram_addr[7].
mem_addr[6] Alternate function: sdram_addr[6].
mem_addr[5] Alternate function: sdram_addr[5].
mem_addr[4] Alternate function: sdram_addr[4].
mem_addr[3] Alternate function: sdram_addr[3].
mem_addr[2] Alternate function: sdram_addr[2].
mem_cs_n[5:0]
mem_oe_n
mem_we_n[3:0]
Output
Output
Output
H
H
H
Low
High
High
Memory Chip Select Negated
Recommend an external pull-up.
Signals that a Memory Bank is actively selected.
Memory Output Enable Negated
Recommend an external pull-up.
Signals that a Memory Bank can output its data lines onto the cpu_ad bus.
Memory Write Enable Negated Bus
Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and
mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.
Table 1 Pin Descriptions (Part 1 of 6)
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May 2, 2002
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