Hitachi SuperH™ RISC engine
SH7040 Series
Hardware Manual
ADE-602-117D
Rev. 5.0
3/19/00
Hitachi, Ltd.
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Preface
The SH7040 Series (SH7040, SH7041, SH7042, SH7043, SH7044, SH7045) single-chip RISC
(Reduced Instruction Set Computer) microprocessors integrate a Hitachi-original RISC CPU core
with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle,
which greatly improves instruction execution speed. In addition, the 32-bit internal-bus
architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds. In
particular, the SH7040 series has a 1-kbyte on-chip cache, which allows an improvement in CPU
performance during external memory access.
In addition, the SH7040 series includes on-chip peripheral functions necessary for system
configuration, such as large-capacity ROM and RAM, timers, a serial communication interface
(SCI), an A/D converter, an interrupt controller, and I/O ports. Memory or peripheral LSIs can be
connected efficiently with an external memory access support function. This greatly reduces
system cost.
There are versions of on-chip ROM: mask ROM, PROM, and flash memory. The flash memory
can be programmed with a programmer that supports SH7040 series programming, and can also
be programmed and erased by software.
This hardware manual describes the SH7040 series hardware. Refer to the programming manual
for a detailed description of the instruction set.
Related Manual
SH7040 series instructions
SH-1/SH-2/SH-DSP Programming Manual
Please consult your Hitachi sales representative for details for development environment system.
Contents
Section 1
1.1
1.2
1.3
SH7040 Series Overview
.............................................................................
1.4
SH7040 Series Overview ..................................................................................................
1.1.1 SH7040 Series Features........................................................................................
Block Diagram...................................................................................................................
Pin Arrangement and Pin Functions..................................................................................
1.3.1 Pin Arrangment ....................................................................................................
1.3.2 Pin Arrangement by Mode ...................................................................................
1.3.3 Pin Functions........................................................................................................
The F-ZTAT Version Onboard Programming ..................................................................
1
1
1
11
13
13
16
37
42
Section 2
2.1
CPU
..................................................................................................................... 45
45
45
46
47
47
48
48
48
48
49
49
52
56
59
72
72
74
2.2
2.3
2.4
2.5
Register Configuration ......................................................................................................
2.1.1 General Registers (Rn) .........................................................................................
2.1.2 Control Registers..................................................................................................
2.1.3 System Registers ..................................................................................................
2.1.4 Initial Values of Registers ....................................................................................
Data Formats......................................................................................................................
2.2.1 Data Format in Registers......................................................................................
2.2.2 Data Format in Memory .......................................................................................
2.2.3 Immediate Data Format........................................................................................
Instruction Features ...........................................................................................................
2.3.1 RISC-Type Instruction Set ...................................................................................
2.3.2 Addressing Modes................................................................................................
2.3.3 Instruction Format ................................................................................................
Instruction Set by Classification........................................................................................
Processing States ...............................................................................................................
2.5.1 State Transitions ...................................................................................................
2.5.2 Power-Down State................................................................................................
Section 3
3.1
3.2
3.3
Operating Modes
............................................................................................ 77
Operating Modes, Types, and Selection............................................................................ 77
Explanation of Operating Modes....................................................................................... 78
Pin Configuration .............................................................................................................. 79
Section 4
4.1
4.2
Clock Pulse Generator (CPG)
..................................................................... 81
Overview............................................................................................................................ 81
4.1.1 Block Diagram...................................................................................................... 81
Oscillator............................................................................................................................ 81
4.2.1 Connecting a Crystal Oscillator............................................................................ 81
i
4.3
4.4
4.2.2 External Clock Input Method ............................................................................... 82
4.2.3 Notes on Board Design ........................................................................................ 83
Prescaler ............................................................................................................................ 84
Oscillator Halt Function .................................................................................................... 84
Section 5
5.1
Exception Processing
..................................................................................... 85
85
85
86
87
88
89
89
90
91
91
92
92
92
93
93
94
94
94
94
95
96
96
96
96
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Overview............................................................................................................................
5.1.1 Types of Exception Processing and Priority ........................................................
5.1.2 Exception Processing Operations .........................................................................
5.1.3 Exception Processing Vector Table......................................................................
Resets.................................................................................................................................
5.2.1 Power-On Reset....................................................................................................
5.2.2 Manual Reset........................................................................................................
Address Errors ...................................................................................................................
5.3.1 Address Error Exception Processing....................................................................
Interrupts............................................................................................................................
5.4.1 Interrupt Priority Level.........................................................................................
5.4.2 Interrupt Exception Processing ............................................................................
Exceptions Triggered by Instructions................................................................................
5.5.1 Trap Instructions ..................................................................................................
5.5.2 Illegal Slot Instructions ........................................................................................
5.5.3 General Illegal Instructions ..................................................................................
When Exception Sources Are Not Accepted.....................................................................
5.6.1 Immediately after a Delayed Branch Instruction..................................................
5.6.2 Immediately after an Interrupt-Disabled Instruction............................................
Stack Status after Exception Processing Ends...................................................................
Notes on Use......................................................................................................................
5.8.1 Value of Stack Pointer (SP)..................................................................................
5.8.2 Value of Vector Base Register (VBR) .................................................................
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing......
Section 6
6.1
Interrupt Controller (INTC)
......................................................................... 97
97
97
97
99
99
100
100
100
100
101
101
6.2
Overview ...........................................................................................................................
6.1.1 Features ................................................................................................................
6.1.2 Block Diagram......................................................................................................
6.1.3 Pin Configuration .................................................................................................
6.1.4 Register Configuration .........................................................................................
Interrupt Sources................................................................................................................
6.2.1 NMI Interrupts......................................................................................................
6.2.2 User Break Interrupt .............................................................................................
6.2.3 IRQ Interrupts ......................................................................................................
6.2.4 On-Chip Peripheral Module Interrupts ................................................................
6.2.5 Interrupt Exception Vectors and Priority Rankings .............................................
ii
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