Document Revision History
Version History
Rev 0
Rev 1.0
Initial release
Fixed typos in Section 1.1.3, Replace any reference to Flash Interface Unit with Flash Module,
corrected pin number for D14 in
Table 2-2,
added note to Vcap pin in
Table 2-2,
corrected
thermal numbers for 160 LQFP in
Table 10-4,removed
unneccessary notes in
Table 10-13;
corrected temperature range in
Table 10-14;
added ADC calibration information to
Table 10-24
and new graphs in
Figure 10-22.
Clarification to
Table 10-23,
corrected Digital Input Current Low (pull-up enabled)
numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8147 information; edited to indicate differences in 56F8347 and 56F8147.
Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updaated balance of electrical tables for consistency throughout the family. Clarified I/O power
description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3.
Correcting
Figure 4-1
Boot Flash Start = $02_0000
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Added 160MAPBGA information, TA equation updated in
Table 10-4
and additional minor edits
throughout data sheet
Updated
Table 10-24
to reflect new value for maximum Uncalibrated Gain Error
Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient
Operating Temperature (Industrial) and corrected Flash Endurance to 10,000 in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Corrected
Section 6.4
title (from Operation Mode Register to Operating Mode Register).
Updated JTAG ID in
Section 6.5.4.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crystal frequency for PLL in
Table 10-14
by increasing maximum
value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging
environment, TRST may be tied to V
SS
through a 1K resistor.
Description of Change
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev. 11
Please see http://www.freescale.com for the most current data sheet revision.
56F8347 Technical Data, Rev.11
2
Freescale Semiconductor
Preliminary
56F8347/56F8147 General Description
Note:
Features in italics are NOT available in the 56F8147 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB of
data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package and
160MAPBGA
RSTO
EMI_MODE
EXTBOOT
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP*
4
OCR_DIS
V
DD
V
SS
7
6
Digital Reg
V
DDA
2
V
SSA
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
* Configuration
shown for on-chip
2.5V regulator
PWMA
Analog Reg
Current Sense Inputs or
GPIOC
Fault Inputs
PWM Outputs
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Current Sense Inputs or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
AD1
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 Æ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
ADCB
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
Boot ROM
4K x 16 Flash
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
6
2
External
Address Bus
Switch
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0 or GPIOD8)
DS (CS1 or GPIOD9)
**See Table 2-2
for explanation
Temp_Sense
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
8
4
1
3
4
D
ata Memory
4K x 16 RAM
4K x 16 Flash
External Bus
Interface Unit
System Bus
Control
External Data
Bus Switch
7
9
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
Bus Control
6
2
Decoding
Peripherals
Clock
resets
PLL
2
2
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8347/56F8147 Block Diagram
56F8347 Technical Data, Rev.11
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8347/56F8147 Features . . . . . . . . . . . . . 5
Device Description . . . . . . . . . . . . . . . . . . . . 7
Award-Winning Development Environment . 9
Architecture Block Diagram . . . . . . . . . . . . . 10
Product Documentation . . . . . . . . . . . . . . . . 14
Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 123
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 123
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 123
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 123
Part 9: Joint Test Action Group (JTAG) . 128
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 128
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 10: Specifications. . . . . . . . . . . . . . . . 128
10.1. General Characteristics. . . . . . . . . . . . . . 128
10.2. DC Electrical Characteristics . . . . . . . . . . 132
10.3. AC Electrical Characteristics . . . . . . . . . . 136
10.4. Flash Memory Characteristics. . . . . . . . . 136
10.5. External Clock Operation Timing . . . . . . 137
10.6. Phase Locked Loop Timing. . . . . . . . . . . . 137
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 138
10.8. External Memory Interface Timing . . . . . . 138
10.9. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . . . . 141
10.10. Serial Peripheral Interface (SPI) Timing . 143
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 147
10.12. Quadrature Decoder Timing . . . . . . . . . . 147
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . 148
10.14. Controller Area Network (CAN) Timing . 149
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 149
10.16. Analog-to-Digital Converter
(ADC) Parameter . . . . . . . . . . . . 151
10.17. Equivalent Circuit for ADC Inputs . . . . . 154
10.18. Power Consumption . . . . . . . . . . . . . . . 154
Part 3: On-Chip Clock Synthesis (OCCS) . 38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Program Map. . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers . . . .
Factory Programmed Memory. . . . . . . . . . .
40
41
42
45
46
47
48
73
Part 5: Interrupt Controller (ITCN) . . . . . . . 74
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 74
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Functional Description . . . . . . . . . . . . . . . . 74
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 76
Operating Modes . . . . . . . . . . . . . . . . . . . . 76
Register Descriptions . . . . . . . . . . . . . . . . . 77
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 156
11.1. 56F8347 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 156
11.2. 56F8147 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 163
Part 6: System Integration Module (SIM) . 103
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . .
Operating Mode Register . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . .
Clock Generation Overview. . . . . . . . . . . .
Power-Down Modes Overview . . . . . . . . .
Stop and Wait Mode Disable Function . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
103
104
104
105
118
118
119
119
Part 12: Design Considerations . . . . . . . . 167
12.1. Thermal Design Considerations . . . . . . . . 167
12.2. Electrical Design Considerations . . . . . . . 168
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . 169
Part 13: Ordering Information . . . . . . . . . . 170
Part 7: Security Features . . . . . . . . . . . . . . 120
7.1. Operation with Security Enabled . . . . . . . 120
7.2. Flash Access Blocking Mechanisms . . . . . 120
56F8347 Technical Data, Rev.11
4
Freescale Semiconductor
Preliminary
56F8347/56F8147 Features
Part 1 Overview
1.1 56F8347/56F8147 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Core
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8347 and 56F8147 devices.
Table 1-1 Device Differences
Feature
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
56F8347
60MHz/60 MIPS
4KB
8KB
2x6
1
4
2x4
1
—
56F8147
40MHZ/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
7
56F8347 Technical Data, Rev.11
Freescale Semiconductor
Preliminary
5
FPGA/CPLD
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