Document Revision History
Version History
Rev. 0
Rev. 1
Initial public release.
• In
Table 10-4,
added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In
Table 10-6,
changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In
Table 10-12,
changed the typical relaxation oscillator output frequency in Standby
mode from 400kHz to 200kHz.
• Changed input propagation delay values in
Table 10-20
as follows:
Old values: 1
μs
typical, 2
μs
maximum
New values: 35 ns typical, 45 ns maximum
Rev. 2
In
Table 10-19,
changed the maximum ADC internal clock frequency from 8 MHz to 5.33
MHz.
• Added the following note to the description of the TMS signal in
Table 2-3:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
Old labels: Pin 1, Pin 12, Pin 23, Pin 34
New labels: Pin 1, Pin 9, Pin 17, Pin 25
• Corrected pin number labels in
Figure 11-1
as follows:
Description of Change
Rev. 3
Please see http://www.freescale.com for the most current data sheet revision.
56F8023 Data Sheet, Rev. 3
2
Freescale Semiconductor
Preliminary
56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB (16K x 16) Program Flash
• 4KB (2K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET or
GPIOA
4
JTAG/EOnCE
Port or
GPIOD
V
CAP
V
DD
V
SS
2
V
DDA
V
SSA
5
Digital Reg
Analog Reg
PWM
or TMRA or GPIOA
Program Controller
and Hardware
Looping Unit
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
DAC
4
PAB
PDB
CDBR
CDBW
AD0
ADC
or CMP
or GPIOC
Memory
Program Memory
16K x 16 Flash
Unified Data /
Program RAM
2K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
4
AD1
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I
2
C
or CMP
or GPIOB
QSPI
or PWM
or I
2
C
or TMRA
or GPIOB
4
QSCI
or PWM
or I
2
C
or TMRA
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
2
*Includes On-Chip
Relaxation Oscillator
56F8023 Block Diagram
56F8023 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
3
56F8023 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8023 Features . . . . . . . . . . . . . . . . . . . . . 5
56F8023 Description . . . . . . . . . . . . . . . . . . . 7
Award-Winning Development Environment . . 8
Architecture Block Diagram . . . . . . . . . . . . . 8
Product Documentation . . . . . . . . . . . . . . . . 16
Data Sheet Conventions. . . . . . . . . . . . . . . 16
Part 8: General-Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 106
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 106
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 106
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 108
Part 9: Joint Test Action Group (JTAG) . .113
9.1. 56F8023 Information . . . . . . . . . . . . . . . . . 113
Part 2: Signal/Connection Descriptions . . 17
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. 56F8023 Signal Pins . . . . . . . . . . . . . . . . . . 21
Part 10: Specifications. . . . . . . . . . . . . . . . 113
10.1. General Characteristics . . . . . . . . . . . . . . 113
10.2. DC Electrical Characteristics . . . . . . . . . . 117
10.3. AC Electrical Characteristics . . . . . . . . . . 120
10.4. Flash Memory Characteristics . . . . . . . . . 121
10.5. External Clock Operation Timing . . . . . . . 121
10.6. Phase Locked Loop Timing . . . . . . . . . . . 122
10.7. Relaxation Oscillator Timing. . . . . . . . . . . 122
10.8. Reset, Stop, Wait, Mode Select,
and Interrupt Timing. . . . . . . . . . . 124
10.9. Serial Peripheral Interface (SPI) Timing . 125
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 128
10.11. Serial Communication Interface
(SCI) Timing. . . . . . . . . . . . . . . . . 129
10.12. Inter-Integrated Circuit Interface
(I2C) Timing . . . . . . . . . . . . . . . . . 130
10.13. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 131
10.14. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . . 133
10.15. Equivalent Circuit for ADC Inputs . . . . . . 134
10.16. Comparator (CMP) Parameters . . . . . . . 134
10.17. Digital-to-Analog Converter
(DAC) Parameters . . . . . . . . . . . . 135
10.18. Power Consumption . . . . . . . . . . . . . . . 136
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 30
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating Modes . . . . . . . . . . . . . . . . . . . . . 30
Internal Clock Source . . . . . . . . . . . . . . . . . 31
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . 31
Ceramic Resonator. . . . . . . . . . . . . . . . . . . 32
External Clock Input - Crystal
Oscillator Option . . . . . . . . . . . . . . 32
3.8. Alternate External Clock Input . . . . . . . . . . 33
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
Part 4: Memory Maps . . . . . . . . . . . . . . . . . . 33
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt Vector Table . . . . . . . . . . . . . . . . . 34
Program Map . . . . . . . . . . . . . . . . . . . . . . . 36
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EOnCE Memory Map . . . . . . . . . . . . . . . . . . 37
Peripheral Memory-Mapped Registers . . . . 38
Part 5: Interrupt Controller (ITCN) . . . . . . . 51
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 51
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Functional Description . . . . . . . . . . . . . . . . 52
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 54
Operating Modes . . . . . . . . . . . . . . . . . . . . 54
Register Descriptions . . . . . . . . . . . . . . . . . . 54
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 138
11.1. 56F8023 Package and
Pin-Out Information . . . . . . . . . . . 138
Part 12: Design Considerations . . . . . . . . .141
12.1. Thermal Design Considerations . . . . . . . . 141
12.2. Electrical Design Considerations . . . . . . . 142
Part 6: System Integration Module (SIM). . 74
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 74
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Register Descriptions . . . . . . . . . . . . . . . . . 75
Clock Generation Overview . . . . . . . . . . . . 99
Power-Saving Modes . . . . . . . . . . . . . . . . 100
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Part 13: Ordering Information . . . . . . . . . . 143
Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 144
Part 7: Security Features . . . . . . . . . . . . . 104
7.1. Operation with Security Enabled . . . . . . . . 104
7.2. Flash Access Lock and
Unlock Mechanisms . . . . . . . . . . 105
56F8023 Data Sheet, Rev. 3
4
Freescale Semiconductor
Preliminary
56F8023 Features
Part 1 Overview
1.1 56F8023 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2
•
•
•
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
On-chip memory
— 32KB of Program Flash
— 4KB of Unified Data/Program RAM
EEPROM emulation capability using Flash
•
1.1.3
•
Peripheral Circuits for 56F8023
One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
56F8023 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
5
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