56F8037 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 8-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• Two Queued Serial Communication Interfaces (QSCIs)
with LIN slave functionality
• Two Queued Serial Peripheral Interfaces (QSPIs)
RESET or
GPIOA
4
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• Two 16-bit Quad Timers
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 53 GPIO lines
• 64-pin LQFP Package
V
CAP
2
V
DD
3
V
SS
4
V
DDA
V
SSA
14
PWM
or TMRA or TMRB
or CMP or QSPI1
or GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
2
DAC
or GPIOD
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
8
PAB
PDB
CDBR
CDBW
AD0
ADC
or CMP
or QSCI1
or GPIOC
AD1
Memory
Program Memory
32K x 16 Flash
Unified Data /
Program RAM
4K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
8
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I
2
C
or CAN
or TMRB
or CMP
or GPIOB
6
QSPI0
or PWM
or I
2
C
or TMRA
or GPIOB
QSCI0
or PWM
or I
2
C
or QSPI1
or TMRA
or TMRB
or GPIOB
4
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
4
*Includes On-Chip
Relaxation Oscillator
56F8037 Block Diagram
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
3
56F8037 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8037 Features . . . . . . . . . . . . . . . . . . . . 5
56F8037 Description . . . . . . . . . . . . . . . . . . . 7
Award-Winning Development Environment . 8
Architecture Block Diagram . . . . . . . . . . . . . 8
Product Documentation . . . . . . . . . . . . . . . 16
Data Sheet Conventions. . . . . . . . . . . . . . . 16
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .127
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 127
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 131
Part 9: Joint Test Action Group (JTAG) . .136
9.1. 56F8037 Information . . . . . . . . . . . . . . . . . 136
Part 2: Signal/Connection Descriptions . . 17
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. 56F8037 Signal Pins . . . . . . . . . . . . . . . . . 22
Part 10: Specifications . . . . . . . . . . . . . . . .136
10.1. General Characteristics . . . . . . . . . . . . . . 136
10.2. DC Electrical Characteristics . . . . . . . . . . 140
10.3. AC Electrical Characteristics . . . . . . . . . . 143
10.4. Flash Memory Characteristics . . . . . . . . . 143
10.5. External Clock Operation Timing . . . . . . . 144
10.6. Phase Locked Loop Timing . . . . . . . . . . . 145
10.7. Relaxation Oscillator Timing. . . . . . . . . . . 145
10.8. Reset, Stop, Wait, Mode Select,
and Interrupt Timing. . . . . . . . . . . 147
10.9. Serial Peripheral Interface (SPI) Timing . 148
10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 151
10.11. Queued Serial Communication
Interface (QSCI) Timing . . . . . . . . 152
10.12. Freescale’s Scalable Controller Area
Network (MSCAN) Timing . . . . . . 153
10.13. Inter-Integrated Circuit Interface
(I2C) Timing . . . . . . . . . . . . . . . . . 153
10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 155
10.15. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . . 156
10.16. Equivalent Circuit for ADC Inputs . . . . . 157
10.17. Comparator (CMP) Parameters . . . . . . . 157
10.18. Digital-to-Analog Converter
(DAC) Parameters . . . . . . . . . . . . 158
10.19. Power Consumption . . . . . . . . . . . . . . . . 159
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 38
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating Modes . . . . . . . . . . . . . . . . . . . . 39
Internal Clock Source . . . . . . . . . . . . . . . . . 40
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . 40
Ceramic Resonator. . . . . . . . . . . . . . . . . . . 41
External Clock Input - Crystal
Oscillator Option. . . . . . . . . . . . . . 41
3.8. Alternate External Clock Input . . . . . . . . . . . 42
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
Part 4: Memory Maps . . . . . . . . . . . . . . . . . 42
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
Program Map . . . . . . . . . . . . . . . . . . . . . . . 45
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EOnCE Memory Map . . . . . . . . . . . . . . . . . 46
Peripheral Memory-Mapped Registers . . . . 47
Part 5: Interrupt Controller (ITCN) . . . . . . . . 64
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 64
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Functional Description . . . . . . . . . . . . . . . . . 64
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 66
Operating Modes . . . . . . . . . . . . . . . . . . . . . 67
Register Descriptions . . . . . . . . . . . . . . . . . . 67
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 161
11.1. 56F8037 Package and
Pin-Out Information . . . . . . . . . . . 161
Part 6: System Integration Module (SIM) . . 89
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 89
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Register Descriptions . . . . . . . . . . . . . . . . . 91
Clock Generation Overview . . . . . . . . . . . . 120
Power-Saving Modes . . . . . . . . . . . . . . . . . 120
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 125
Part 12: Design Considerations . . . . . . . . 164
12.1. Thermal Design Considerations . . . . . . . 164
12.2. Electrical Design Considerations . . . . . . . 165
Part 13: Ordering Information . . . . . . . . . . 166
Part 14: Appendix . . . . . . . . . . . . . . . . . . . .167
Part 7: Security Features . . . . . . . . . . . . . 125
7.1. Operation with Security Enabled . . . . . . . . 125
7.2. Flash Access Lock and
Unlock Mechanisms . . . . . . . . . . 126
56F8037 Data Sheet, Rev. 3
4
Freescale Semiconductor
Preliminary
56F8037 Features
Part 1 Overview
1.1 56F8037 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2
•
•
•
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
On-chip memory
— 64KB of Program Flash
— 8KB of Unified Data/Program RAM
EEPROM emulation capability using Flash
•
1.1.3
•
Peripheral Circuits for 56F8037
One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and Edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
5
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