74LVC1G53
2-channel analog multiplexer/demultiplexer
Rev. 9 — 5 April 2013
Product data sheet
1. General description
The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire V
CC
range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5
(typical) at V
CC
= 2.7 V
6.5
(typical) at V
CC
= 3.3 V
6
(typical) at V
CC
= 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Control inputs accept voltages up to 5 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G53DP
40 C
to +125
C
74LVC1G53DC
40 C
to +125
C
74LVC1G53GT
40 C
to +125
C
74LVC1G53GF
40 C
to +125
C
74LVC1G53GD
40 C
to +125
C
74LVC1G53GM
40 C
to +125
C
74LVC1G53GN
40 C
to +125
C
74LVC1G53GS
40 C
to +125
C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-2
SOT1116
SOT1203
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
V53
V53
V53
V3
V53
V53
V3
V3
Type number
74LVC1G53DC
74LVC1G53DP
74LVC1G53GT
74LVC1G53GF
74LVC1G53GD
74LVC1G53GM
74LVC1G53GN
74LVC1G53GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Y1
Y0
E
S
Z
001aah795
Fig 1.
74LVC1G53
Logic symbol
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 5 April 2013
2 of 27
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
Y0
S
Z
Y1
E
001aad387
Fig 2.
Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G53
Z
1
8
V
CC
E
2
7
Y0
74LVC1G53
GND
Z
E
GND
GND
1
2
3
4
001aad388
3
6
Y1
8
7
6
5
V
CC
Y0
Y1
S
GND
4
5
S
001aad389
Transparent top view
Fig 3.
Pin configuration SOT505-2 and SOT765-1
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 5 April 2013
3 of 27
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
74LVC1G53
terminal 1
index area
Y0
1
V
CC
8
74LVC1G53
Z
E
GND
GND
1
2
3
4
8
7
6
5
V
CC
7
Z
Y1
Y0
Y1
S
S
2
6
E
3
4
5
GND
GND
001aag459
001aai249
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2
Fig 6.
Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
Z
E
GND
GND
S
Y1
Y0
V
CC
1
2
3
4
5
6
7
8
SOT902-2
7
6
5
4
3
2
1
8
common output or input
enable input (active LOW)
ground (0 V)
ground (0 V)
select input
independent input or output
independent input or output
supply voltage
Description
7. Functional description
Table 4.
Input
S
L
H
X
[1]
Function table
[1]
Channel on
E
L
L
H
Y0 to Z or Z to Y0
Y1 to Z or Z to Y1
Z (switch off)
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 5 April 2013
4 of 27
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
SK
V
SW
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
input clamping current
switch clamping current
switch voltage
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
50
-
[2]
Max
+6.5
+6.5
-
50
V
CC
+ 0.5
50
100
-
+150
250
Unit
V
V
mA
mA
V
mA
mA
mA
C
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
enable and disable mode
V
SW
>
0.5
V or V
SW
< V
CC
+ 0.5 V
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed.
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
For TSSOP8 packages: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
[1]
[2]
[2]
Conditions
Min
1.65
0
Max
5.5
5.5
V
CC
+125
20
10
Unit
V
V
V
C
ns/V
ns/V
enable and disable mode
[1]
0
40
-
-
To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
Applies to control signal levels.
[2]
74LVC1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 5 April 2013
5 of 27
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