74LV4051
8-channel analog multiplexer/demultiplexer
Rev. 7 — 9 October 2018
Product data sheet
1. General description
The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs
(S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
a common input/output (Z). It is a low-voltage Si-gate CMOS device that is pin and function
compatible with 74HC4051 and 74HCT4051. With E LOW, one of the eight switches is selected
(low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the high-impedance
OFF-state, independent of S0 to S2.
V
CC
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The V
CC
to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between
V
CC
as a positive limit and V
EE
as a negative limit. V
CC
- V
EE
may not exceed 6.0 V. For operation
as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically ground).
2. Features and benefits
•
•
•
Optimized for low-voltage applications: 1.0 V to 6.0 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low ON resistance:
•
145 Ω (typical) at V
CC
- V
EE
= 2.0 V
•
80 Ω (typical) at V
CC
- V
EE
= 3.0 V
•
60 Ω (typical) at V
CC
- V
EE
= 4.5 V
Logic level translation:
•
To enable 3 V logic to communicate with ±3 V analog signals
Typical ‘break before make’ built in
ESD protection:
•
HBM JESD22-A114E exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LV4051D
74LV4051DB
74LV4051PW
74LV4051BQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Nexperia
74LV4051
8-channel analog multiplexer/demultiplexer
4. Functional diagram
V
CC
16
13 Y0
S0 11
14 Y1
15 Y2
S1 10
12 Y3
LOGIC
LEVEL
CONVERSION
S2 9
1-OF-8
DECODER
1 Y4
5 Y5
2 Y6
E 6
4 Y7
3 Z
8
GND
7
V
EE
001aad543
Fig. 1.
Functional diagram
11
10
9
6
0
2
G8
8X
0
7
13
S0
S1
S2
11
10
9
14
15
12
1
5
2
E
6
3
Z
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3
MUX/DMUX
0
1
2
3
4
5
6
7
13
14
15
12
1
5
2
4
001aad541
001aad542
Fig. 2.
Logic symbol
Fig. 3.
IEC logic symbol
74LV4051
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 7 — 9 October 2018
2 / 22
Nexperia
74LV4051
8-channel analog multiplexer/demultiplexer
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Fig. 4.
Schematic diagram (one switch)
5. Pinning information
5.1. Pinning
74LV4051
Y4
Y6
Z
Y7
Y5
E
V
EE
GND
1
2
3
4
5
6
7
8
aaa-029146
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
9
S2
74LV4051
Y4
Y6
Z
Y7
Y5
E
V
EE
GND
1
2
3
4
5
6
7
8
001aak407
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
9
S2
Fig. 5.
Pin configuration SOT109-1 (SO16)
Fig. 6.
Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
74LV4051
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 7 — 9 October 2018
3 / 22
Nexperia
74LV4051
8-channel analog multiplexer/demultiplexer
74LV4051
terminal 1
index area
Y6
Z
Y7
Y5
E
V
EE
2
3
4
5
6
7
8
GND
S2
9
V
CC(1)
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
Y4
1
001aak408
Transparent top view
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig. 7.
Pin configuration SOT763-1 (DHVQFN16)
5.2. Pin description
Table 2. Pin description
Symbol
E
V
EE
GND
S0, S1, S2
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
Z
V
CC
Pin
6
7
8
11, 10, 9
13, 14, 15, 12, 1, 5, 2, 4
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
E
L
L
L
L
L
L
L
L
H
S2
L
L
L
L
H
H
H
H
X
S1
L
L
H
H
L
L
H
H
X
S0
L
H
L
H
L
H
L
H
X
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
switches off
Channel ON
74LV4051
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 7 — 9 October 2018
4 / 22
Nexperia
74LV4051
8-channel analog multiplexer/demultiplexer
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND = 0 V.
Symbol Parameter
V
CC
I
IK
I
SK
I
SW
T
stg
P
tot
[1]
[2]
[3]
Conditions
[1]
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
SW
< -0.5 V or V
SW
> V
CC
+ 0.5 V
V
SW
> -0.5 V or V
SW
< V
CC
+ 0.5 V;
source or sink current
T
amb
= -40 °C to +125 °C
[2]
[2]
[2]
Min
-0.5
-
-
-
-65
[3]
-
Max
+7.0
±20
±20
±25
+150
500
Unit
V
mA
mA
mA
°C
mW
supply voltage
input clamping current
switch clamping current
switch current
storage temperature
total power dissipation
To avoid drawing V
CC
current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed V
CC
or V
EE
.
The minimum input voltage rating may be exceeded if the input current rating is observed.
For SO16 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of P
tot
derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
V
SW
T
amb
Δt/ΔV
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
[1]
Conditions
see
Fig. 8
[1]
Min
1
0
0
-40
-
-
-
Typ
3.3
-
-
-
-
-
-
Max
6
V
CC
V
CC
+125
500
200
100
Unit
V
V
V
°C
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to 6.0 V, but LV devices are guaranteed to function down to V
CC
= 1.0 V
(with input levels GND or V
CC
).
74LV4051
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 7 — 9 October 2018
5 / 22
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