Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FEATURES
•
5 V tolerant inputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Demultiplexing capability
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Active LOW mutually exclusive outputs
•
Output drive capability 50
Ω
transmission lines at
125
°C
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay An to Yn
propagation delay E3 to Yn
propagation delay En to Yn
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
DESCRIPTION
74LVC138A
The 74LVC138A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC138A accepts three binary weighted address
inputs (A0, A1 and A2) and when enabled, provides 8
mutually exclusive active LOW outputs (Y0 to Y7).
The 74LVC138A features three enable inputs: two active
LOW (E1 and E2) and one active HIGH (E3). Every output
will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines)
decoder with just four 74LVC138A ICs and one inverter.
The 74LVC138A can be used as an eight output
demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied
to their appropriate active HIGH or LOW state.
TYPICAL
2.6
2.8
2.7
4.0
21
ns
ns
ns
pF
pF
UNIT
2003 May 06
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
A1
A2
E1
E2
E3
Y7
GND
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V
CC
SYMBOL
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
output
ground (0 V)
output
output
output
output
output
output
output
supply voltage
DESCRIPTION
74LVC138A
handbook, halfpage
handbook, halfpage
A0
1
VCC
16
15
14
13
Y0
Y1
Y2
Y3
Y4
Y5
A0 1
A1 2
A2 3
E1 4
16 VCC
15 Y0
14 Y1
13 Y2
A1
A2
E1
E2
E3
2
3
4
138
E2 5
E3 6
Y7 7
GND 8
MNA369
12 Y3
11 Y4
GND
(1)
5
6
7
8
Top view
GND
9
Y6
MCE177
12
11
10
10 Y5
9
Y6
Y7
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 May 06
4
嵌入式系统
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