Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
FEATURES
•
5 V tolerant inputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
74LVC109
The 74LVC109A is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC109A is a dual positive edge triggered
JK flip-flop featuring individual J and K inputs, clock (CP)
inputs, set (SD) and reset (RD) inputs and complementary
Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation. The JK design allows operation as a D-type
flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay nCP to nQ
and nCP to nQ
propagation delay nSD to nQ
and nRD to nQ
propagation delay nSD to nQ
and nRD to nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
maximum clock frequency
input capacitance
power dissipation capacitance per
flip-flop
notes 1 and 2
CONDITIONS
C
L
= 50 pF; R
L
= 500
Ω;
V
CC
= 3.3 V
C
L
= 50 pF; R
L
= 500
Ω;
V
CC
= 3.3 V
C
L
= 50 pF; R
L
= 500
Ω;
V
CC
= 3.3 V
C
L
= 50 pF; R
L
= 500
Ω;
V
CC
= 3.3 V
TYPICAL
3.8
3.2
3.5
330
5.0
23
ns
ns
ns
MHz
pF
pF
UNIT
2004 Mar 18
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODES
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L
H
L
H
H
H
H
nRD
H
L
L
H
H
H
H
nCP
X
X
X
↑
↑
↑
↑
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
74LVC109
OUTPUT
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH
CP transition;
X = don’t care;
↑
= LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74LVC109D
74LVC109DB
74LVC109PW
TEMPERATURE
RANGE
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
16
16
16
PACKAGE
SO16
SSOP16
TSSOP16
MATERIAL
plastic
plastic
plastic
CODE
SOT109-1
SOT338-1
SOT403-1
2004 Mar 18
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1RD
1J
1K
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2K
2J
2RD
V
CC
SYMBOL
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set input (active LOW)
clock input (LOW-to-HIGH; edge-triggered)
synchronous input
synchronous input
asynchronous reset input (active LOW)
supply voltage
DESCRIPTION
asynchronous reset input (active LOW)
74LVC109
handbook, halfpage
1RD 1
1J 2
1K 3
1CP 4
16 VCC
15 2RD
14 2J
13 2K
handbook, halfpage
5 11
1SD 2SD
2
14
4
12
3
13
SD
1Q
1J
Q
J
2J
2Q
1CP
CP
2CP
FF
1Q
1K
Q
K
2Q
2K
RD
1RD 2RD
6
10
109
1SD 5
1Q 6
1Q 7
GND 8
MNA855
12 2CP
11 2SD
10 2Q
9 2Q
7
9
1 15
MNA858
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Logic symbol.
2004 Mar 18
4
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