74LV4094
8-stage shift-and-store bus register
Rev. 02 — 29 June 2006
Product data sheet
1. General description
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and function compatible
with 74HC4094, 74HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage latch associated with
each stage for strobing data from the serial input (D) to the parallel buffered 3-state
outputs (QP0 to QP7). The parallel outputs may be connected directly to the common bus
lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift
register is transferred to the storage register when the strobe input (STR) is HIGH. Data in
the storage register appears at the outputs whenever the output enable input (OE) signal
is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of
74LV4094 devices. Data is available at QS1 on the positive-going clock edges to allow
high-speed operation in cascaded systems in which the clock rise time is fast. The same
serial information is available at QS2 on the next negative going clock edge and is for
cascading 74LV4094 devices when the clock rise time is slow.
2. Features
I
I
I
I
I
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V, T
amb
= 25
°C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V, T
amb
= 25
°C
ESD protection:
N
HBM EIA/JESD22-A114-C exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
I
Specified from
−
40
°
C to +85
°
C and
−
40
°
C to +125
°
C
3. Applications
I
Serial-to-parallel data conversion
I
Remote control holding register
Philips Semiconductors
74LV4094
8-stage shift-and-store bus register
4. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LV4094N
74LV4094D
74LV4094DB
74LV4094PW
Name
Description
plastic dual in-line package; 16 leads (300 mil)
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT38-4
SOT338-1
SOT403-1
Type number
−40 °C
to +125
°C
DIP16
−40 °C
to +125
°C
SO16
−40 °C
to +125
°C
SSOP16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
−40 °C
to +125
°C
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
5. Functional diagram
3
CP
1
STR
QS1
QS2
QP0
QP1
QP2
2
D
QP3
QP4
QP5
QP6
QP7
OE
15
7
14
13
12
11
9
10
4
5
6
3
2
1
15
C2
EN3
SRG8
C1/
1D
2D
3
4
5
6
7
14
13
12
11
9
10
001aaf111
001aaf112
Fig 1. Logic symbol
Fig 2. IEC logic symbol
2
3
D
CP
8-STAGE SHIFT
REGISTER
QS2
QS1
STR
8-BIT STORAGE
REGISTER
10
9
1
15
OE
3-STATE OUTPUTS
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
5
6
7
14
13
12
11
001aaf119
Fig 3. Functional diagram
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
2 of 21
Philips Semiconductors
74LV4094
8-stage shift-and-store bus register
STAGE 0
D
D
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
Q
QS1
CP FF
0
CP
CP FF
7
D
CP
latch
Q
QS2
CP
D
CP
Q
D
CP
Q
latch
STR
OE
latch
QP0
QP1 QP2 QP3 QP4 QP5 QP6
QP7
001aaf118
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
74LV4094
STR
D
CP
QP0
QP1
QP2
QP3
GND
1
2
3
4
5
6
7
8
001aaf120
16 V
CC
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
QS1
Fig 5. Pin configuration DIP16, SO16 and (T)SSOP16
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
3 of 21
Philips Semiconductors
74LV4094
8-stage shift-and-store bus register
6.2 Pin description
Table 2.
Symbol
STR
D
CP
QP0
QP1
QP2
QP3
GND
QS1
QS2
QP7
QP6
QP5
QP4
OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
data strobe input
data serial input
clock input (edge triggered LOW-to-HIGH)
data parallel output 0
data parallel output 1
data parallel output 2
data parallel output 3
ground (0 V)
data serial output 1
data serial output 2
data parallel output 7
data parallel output 6
data parallel output 5
data parallel output 4
output enable input
supply voltage
7. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; n.c. = no change;
↑
= LOW-to-HIGH clock transition;
↓
= HIGH-to-LOW clock transition.
Input
CP
↑
↓
↑
↑
↑
↓
[1]
Parallel output
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
QP0
Z
Z
n.c.
L
H
n.c.
QPn
Z
Z
n.c.
QPn−1
QPn−1
n.c.
Serial output
QS1
[1]
QS6
n.c.
QS6
QS6
QS6
n.c.
QS2
n.c.
QP7
n.c.
n.c.
n.c.
QP7
QS6 = the information in the 7th register stage is transferred to the 8th register stage and QS1, QS2 clock edge.
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
4 of 21
Philips Semiconductors
74LV4094
8-stage shift-and-store bus register
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Z-state
Z-state
Fig 6. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
supply voltage
input clamping current
output clamping current
output current
quiescent supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
(T)SSOP16 package
[1]
[2]
[3]
[4]
DIP16 package: P
tot
derates linearly with 12 mW/K above 70
°C.
SO16 package: P
tot
derates linearly with 8 mW/K above 70
°C.
(T)SSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
°C.
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
Min
−0.5
-
-
-
-
-
−65
Max
±20
±50
±25
50
−50
Unit
mA
mA
mA
mA
mA
+7.0 V
+150
°C
750
500
400
mW
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74LV4094_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
5 of 21
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