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74LV393
Dual 4-bit binary ripple counter
Rev. 5 — 8 December 2015
Product data sheet
1. General description
The 74LV393 is a low–voltage Si-gate CMOS device and is pin and function compatible
with 74HC393 and 74HCT393.
The 74LV393 is a dual 4-stage binary ripple counter. Each counter features a clock input
(nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel
outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A
HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the
state of nCP.
2. Features and benefits
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) 0.8 V at V
CC
= 3.3 V, T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) 2 V at V
CC
= 3.3 V, T
amb
= 25
C
Two 4-bit binary counters with individual clocks
Divide-by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Temperature range
74LV393D
74LV393DB
74LV393PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
Description
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT337-1
SOT402-1
Type number Package
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
NXP Semiconductors
74LV393
Dual 4-bit binary ripple counter
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
Fig 4.
State diagram
74LV393
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 8 December 2015
2 of 16
NXP Semiconductors
74LV393
Dual 4-bit binary ripple counter
Fig 5.
Logic diagram (one counter)
5. Pinning information
5.1 Pinning
Fig 6.
Pin configuration SO14
Fig 7.
Pin configuration SSOP14 and TSSOP14
5.2 Pin description
Table 2.
Symbol
1CP, 2CP
1MR, 2MR
1Q0, 1Q1, 1Q2, 1Q3
GND
2Q0, 2Q1, 2Q2, 2Q3
V
CC
Pin description
Pin
1, 13
2, 12
3, 4, 5, 6
7
11, 10, 9, 8
14
Description
clock input (HIGH-to-LOW, edge-triggered)
asynchronous master reset input (active HIGH)
flip-flop output
ground (0 V)
flip-flop output
supply voltage
74LV393
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 8 December 2015
3 of 16
NXP Semiconductors
74LV393
Dual 4-bit binary ripple counter
6. Functional description
Table 3.
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[1]
Count sequence for one counter
[1]
Output
nQ0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
nQ1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
nQ2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
nQ3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14 package
(T)SSOP14 package
[1]
[2]
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
-
-
Max
+4.6
20
50
25
+50
-
+150
500
400
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
74LV393
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 8 December 2015
4 of 16
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